Uncore Manual

Reference Number: 329468-002 175
Uncore Performance Monitoring
R3QPI Performance Monitoring
Table 2-190. R3_Ly_PCI_PMON_BOX_CTL Register – Field Definitions
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Table 2-191. R3_Ly_PCI_PMON_BOX_STATUS Register – Field Definitions
2.10.3.2 R3QPI PMON state - Counter/Control Pairs
The following table defines the layout of the R3QPI performance monitor control registers. The main
task of these configuration registers is to select the event to be monitored by their respective data
counter (.ev_sel, .umask). Additional control bits are provided to shape the incoming events (e.g.
.edge_det, .thresh) as well as provide additional functionality for monitoring software (.rst,.ov_en).
Field Bits Attr
HW
Reset
Val
Description
ig 31:9 RV 0 Ignored
frz 8 WO 0 Freeze.
If set to 1 the counters in this box will be frozen.
ig 7:2 RV 0 Ignored
rst_ctrs 1 WO 0 Reset Counters.
When set to 1, the Counter Registers will be reset to 0.
rst_ctrl 0 WO 0 Reset Control.
When set to 1, the Counter Control Registers will be reset
to 0.
Field Bits Attr
HW
Reset
Val
Description
ig 31:4 RV 0 Ignored
rsv 3 RV 0 Reserved; SW must write to 0 else behavior is undefined.
ov 2:0 RW1C 0 If an overflow is detected from the corresponding
R3_Ly_PCI_PMON_CTR register, it’s overflow bit will be set.
NOTE: Write of ‘1’ will clear the bit.