Uncore Manual

Uncore Performance Monitoring
Uncore Per-Socket Performance Monitoring Control
18 Reference Number: 329468-002
2.1.4 Enabling a New Sample Interval from Frozen Counters
a) Clear all uncore counters: For each box in which counting occurred, set *_PMON_BOX_CTL.rst_ctrs
to 1.
b) Clear all overflow bits. This includes clearing U_MSR_PMON_GLOBAL_STATUS.ov_* as well as any
*_BOX_STATUS registers that have their overflow bits set.
e.g. If counter 3 in QPI Port 1 overflowed, in order to clear the overflow bit software should set
Q_P1_PCI_PMON_BOX_STATUS.ov[3] to 1.
c) Create the next sample: Reinitialize the sample by setting the monitoring data register to (2^48 -
sample_interval). Or set up a new sample interval as outlined in Section 2.1.2, “Setting up a Monitoring
Session”.
d) Re-enable counting: Set U_MSR_PMON_GLOBAL_CTL.unfrz_all to 1.
2.1.5 Global Performance Monitors
Table 2-1. Global Performance Monitoring Control MSRs
2.1.5.1 Global PMON Global Control/Status Registers
The following registers represent state governing all PMUs in the uncore, both to exert global control
and collect box-level information.
U_MSR_PMON_GLOBAL_CTL contains a bit that can freeze (.frz_all) all the uncore counters.
If an overflow is detected in any of the uncore’s PMON registers, it will be summarized in
U_MSR_PMON_GLOBAL_STATUS. This register accumulates overflows sent to it from the other uncore
boxes. To reset these overflow bits, a user must set the corresponding bits in
U_MSR_PMON_GLOBAL_STATUS to 1, which will act to clear them.
MSR Name
MSR
Address
Size
(bits)
Description
U_MSR_PMON_GLOBAL_CONFIG 0x0C06 32 UBox PMON Global Configuration
U_MSR_PMON_GLOBAL_STATUS 0x0C01 32 UBox PMON Global Status
U_MSR_PMON_GLOBAL_CTL 0x0C00 32 UBox PMON Global Control