Uncore Manual

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Uncore Performance Monitoring

UBox Performance Monitoring

20 Reference Number: 329468-002

Table 2-3. U_MSR_PMON_GLOBAL_STATUS Register – Field Definitions

Table 2-4. U_MSR_PMON_GLOBAL_CONFIG Register – Field Definitions

2.2 UBOX PERFORMANCE MONITORING

2.2.1 Overview of the UBox

The UBox serves as the system configuration controller within the physical processor.

In this capacity, the UBox acts as the central unit for a variety of functions:

Field Bits Attr

HW

Reset

Val

Description

rsv 31:27 RV 0 Reserved

ov_rp 26 RW1C 0 Set if overflow is detected from an R2PCIe PMON register.

NOTE: Write of ‘1’ will clear the bit.

ov_rq1 25 RW1C 0 Set if overflow is detected from an R3QPI1 PMON register.

NOTE: Write of ‘1’ will clear the bit.

ov_rq0 24 RW1C 0 Set if overflow is detected from an R3QPI0 PMON register.

NOTE: Write of ‘1’ will clear the bit.

ov_q1 23 RW1C 0 Set if overflow is detected from a QPI1 PMON register.

NOTE: Write of ‘1’ will clear the bit.

ov_q0 22 RW1C 0 Set if overflow is detected from a QPI0 PMON register.

NOTE: Write of ‘1’ will clear the bit.

ov_m1 21 RW1C 0 Set if overflow is detected from an iMC1 PMON register.

NOTE: Write of ‘1’ will clear the bit.

ov_m0 20 RW1C 0 Set if overflow is detected from an iMC0 PMON register.

NOTE: Write of ‘1’ will clear the bit.

ov_h1 19 RW1C 0 Set if overflow is detected from an HA1 PMON register.

NOTE: Write of ‘1’ will clear the bit.

ov_h0 18 RW1C 0 Set if overflow is detected from an HA0 PMON register.

NOTE: Write of ‘1’ will clear the bit.

ov_c[14-0] 17:3 RW1C 0 Set if overflow is detected from a CBo PMON register, 1 bit for

each CBo where bit 5 corresponds CBo 0, etc.

NOTE: Write of ‘1’ will clear the bit.

ov_p 2 RW1C 0 Set if overflow is detected from a PCU PMON register.

NOTE: Write of ‘1’ will clear the bit.

ov_u 1 RW1C 0 Set if overflow is detected from a UBox PMON register.

NOTE: Write of ‘1’ will clear the bit.

ov_u_fixed 0 RW1C 0 Set if overflow is detected from UBox fixed PMON register.

NOTE: Write of ‘1’ will clear the bit.

Field Bits Attr

HW

Reset

Val

Description

rsv 31:4 RV 0 Reserved

num_c 3:0 RW 8 Number of sets of CBo PMON counters.