Uncore Manual

Uncore Performance Monitoring
UBox Performance Monitoring
22 Reference Number: 329468-002
2.2.3.1 UBox Box Level PMON State
The following registers represent the state governing all box-level PMUs in the UBox.
If an overflow is detected from one of the UBox PMON registers, the corresponding bit in the
U_MSR_PMON_BOX_STATUS.ov field will be set. To reset these overflow bits, a user must write a value
of ‘1’ to them (which will clear the bits).
Table 2-5. U_MSR_PMON_BOX_STATUS Register – Field Definitions
2.2.3.2 UBox PMON state - Counter/Control Pairs
The following table defines the layout of the UBox performance monitor control registers. The main task
of these configuration registers is to select the event to be monitored by their respective data counter
(.ev_sel, .umask). Additional control bits are provided to shape the incoming events (e.g. .edge_det,
.thresh) as well as provide additional functionality for monitoring software (.rst).
Table 2-6. U_MSR_PMON_CTL{1-0} Register – Field Definitions
Field Bits Attr
HW
Reset
Val
Description
rsv 31:2 RV 0 Reserved
ov 1:0 RW1C 0 If an overflow is detected from the corresponding UBOX PMON
register, it’s overflow bit will be set.
NOTE: Write of ‘1’ will clear the bit.
Field Bits Attr
HW
Reset
Val
Description
rsv 31:29 RV 0 Reserved
thresh 28:24 RW 0 Threshold used in counter comparison.
rsv 23 RV 0 Reserved. SW must write to 0 else behavior is undefined.
en 22 RW 0 Local Counter Enable.
rsv 21 RV 0 Reserved. SW must write to 0 else behavior is undefined.
ov_en 20 RW 0 When this bit is set to 1 and the corresponding counter
overflows, a the UBox counters exception is sent to the
UBox.
When this bit is asserted and the corresponding counter
overflows, its overflow bit is set in the local status register
(U_MSR_PMON_BOX_STATUS.ov) and the global status
register U_MSR_PMON_GLOBAL_STATUS.ov_u.
rsv 19 RV 0 Reserved
edge_det 18 RW 0 When set to 1, rather than measuring the event in each
cycle it is active, the corresponding counter will increment
when a 0 to 1 transition (i.e. rising edge) is detected.
When 0, the counter will increment in each cycle that the
event is asserted.
NOTE: .edge_det is in series following .thresh. Due to this,
the .thresh field must be set to a non-0 value. For events
that increment by no more than 1 per cycle, set .thresh to
0x1.
rst 17 WO 0 When set to 1, the corresponding counter will be cleared to
0.
rsv 16 RV 0 Reserved. SW must write to 0 else behavior is undefined.