Uncore Manual

Reference Number: 329468-002 23
Uncore Performance Monitoring
UBox Performance Monitoring
The UBox performance monitor data registers are 44-bit wide. A counter overflow occurs when a
carry out from bit 43 is detected. Software can force all uncore counting to freeze after N events by
preloading a monitor with a count value of 2
44
- N and setting the control register to send an overflow
message to the global logic. During the interval of time between overflow and global disable, the
counter value will wrap and continue to collect events.
If accessible, software can continuously read the data registers without disabling event collection.
Table 2-7. U_MSR_PMON_CTR{1-0} Register – Field Definitions
The Global UBox PMON registers also include a fixed counter that increments at UCLK for each cycle
it is enabled.
Table 2-8. U_MSR_PMON_FIXED_CTL Register – Field Definitions
Table 2-9. U_MSR_PMON_FIXED_CTR Register – Field Definitions
umask 15:8 RW 0 Select subevents to be counted within the selected event.
ev_sel 7:0 RW 0 Select event to be counted.
Field Bits Attr
HW
Reset
Val
Description
rsv 63:44 RV 0 Reserved
event_count 43:0 RW-V 0 44-bit performance event counter
Field Bits Attr
HW
Rese
t Val
Description
rsv 31:23 RV 0 Reserved
en 22 RW-V 0 Local Counter Enable
rsv 21 RV 0 Reserved. SW must write to 0 else behavior is undefined.
ov_en 20 RW-V 0 When this bit is set to 1 and the corresponding counter overflows,
a the UBox counters exception is sent to the UBox.
When this bit is asserted and the corresponding counter
overflows, its overflow bit is set in the local status register
(U_MSR_PMON_BOX_STATUS.ov) and the global status register
U_MSR_PMON_GLOBAL_STATUS.ov_u_fixed.
rsv 19:0 RV 0 Reserved
Field Bits Attr
HW
Reset
Val
Description
rsv 63:44 RV 0 Reserved
event_count 43:0 RW-V 0 48-bit performance event counter
Field Bits Attr
HW
Reset
Val
Description