Uncore Manual

Reference Number: 329468-002 33
Uncore Performance Monitoring
Cacheing Agent (Cbo) Performance Monitoring
Table 2-13. Cn_MSR_PMON_BOX_CTL Register – Field Definitions
2.3.3.2 UCBo PMON state - Counter/Control Pairs
The following table defines the layout of the CBo performance monitor control registers. The main
task of these configuration registers is to select the event to be monitored by their respective data
counter (.ev_sel, .umask). Additional control bits are provided to shape the incoming events (e.g.
.edge_det, .thresh) as well as provide additional functionality for monitoring software (.rst).
Table 2-14. Cn_MSR_PMON_CTL{3-0} Register – Field Definitions
The CBo performance monitor data registers are 44b wide. A counter overflow occurs when a carry
out from bit 43 is detected. Software can force all uncore counting to freeze after N events by
preloading a monitor with a count value of 2
44
- N and setting the control register to send an overflow
Field Bits Attr
HW
Reset
Val
Description
rsv 31:18 RV 0 Reserved
rsv 17:16 RV 0 Reserved; SW must write to 1 else behavior is undefined.
rsv 15:9 RV 0 Reserved
frz 8 WO 0 Freeze.
If set to 1 the counters in this box will be frozen.
rsv 7:2 RV 0 Reserved
rst_ctrs 1 WO 0 Reset Counters.
When set to 1, the Counter Registers will be reset to 0.
rst_ctrl 0 WO 0 Reset Control.
When set to 1, the Counter Control Registers will be reset to
0.
Field Bits Attr
HW
Reset
Val
Description
thresh 31:24 RW-V 0 Threshold used in counter comparison.
rsv 23 RV 0 Reserved; SW must write to 0 else behavior is undefined.
en 22 RW-V 0 Local Counter Enable.
rsv 21:20 RV 0 Reserved; SW must write to 0 else behavior is undefined.
tid_en 19 RW-V 0 TID Filter Enable
edge_det 18 RW-V 0 When set to 1, rather than measuring the event in each
cycle it is active, the corresponding counter will increment
when a 0 to 1 transition (i.e. rising edge) is detected.
When 0, the counter will increment in each cycle that the
event is asserted.
NOTE: .edge_det is in series following .thresh. Due to this,
the .thresh field must be set to a non-0 value. For events
that increment by no more than 1 per cycle, set .thresh to
0x1.
rst 17 WO 0 When set to 1, the corresponding counter will be cleared to
0.
rsv 16 RV 0 Reserved. SW must write to 0 else behavior is undefined.
umask 15:8 RW-V 0 Select subevents to be counted within the selected event.
ev_sel 7:0 RW-V 0 Select event to be counted.