Uncore Manual

Reference Number: 329468-002 55
Uncore Performance Monitoring
Home Agent (HA) Performance Monitoring
For information on how to setup a monitoring session, refer to Section 2.1, “Uncore Per-Socket
Performance Monitoring Control”.
2.4.2.1 HA PMON Registers - On Overflow and the Consequences (PMI/Freeze)
If a overflow is detected from an HA performance counter enabled to communicate its overflow
(HAn_PCI_PMON_CTL.ov_en is set to 1), the overflow bit is set at the box level
(HAn_PCI_PMON_BOX_STATUS.ov) and an overflow message is sent to the UBox. When the UBox
receives the overflow signal, the U_MSR_PMON_GLOBAL_STATUS.ov_h bit is set (see Table 2-3,
“U_MSR_PMON_GLOBAL_STATUS Register – Field Definitions”) and a PMI can be generated.
Once a freeze has occurred, in order to see a new freeze, the overflow responsible for the freeze,
must be cleared by setting the corresponding bit in HAn_PCI_PMON_BOX_STATUS.ov and
U_MSR_PMON_GLOBAL_STATUs.ov_h to 1. Assuming all the counters have been locally enabled (.en
bit in control registers meant to monitor events) and the overflow bit(s) has been cleared, the HA is
prepared for a new sample interval. Once the global controls have been re-enabled (Section 2.1.4,
“Enabling a New Sample Interval from Frozen Counters”), counting will resume.
2.4.2.2 HA Performance Monitors
Table 2-37. HA Performance Monitoring MSRs
2.4.2.3 HA Box Level PMON State
The following registers represent the state governing all box-level PMUs in the HA Box.
Register Name
PCICFG
Address
Size
(bits)
Description
PCICFG Base Address Dev:Func
HA0 PMON Registers D14:F1
HA1 PMON Registers D28:F1
Box-Level Control/Status
HAn_PCI_PMON_BOX_STATUS F8 32 HA n PMON Box-Wide Status
HAn_PCI_PMON_BOX_CTL F4 32 HA n PMON Box-Wide Control
Generic Counter Control
HAn_PCI_PMON_CTL3 E4 32 HA n PMON Control for Counter 3
HAn_PCI_PMON_CTL2 E0 32 HA n PMON Control for Counter 2
HAn_PCI_PMON_CTL1 DC 32 HA n PMON Control for Counter 1
HAnnPCI_PMON_CTL0 D8 32 HA n PMON Control for Counter 0
Generic Counters
HAn_PCI_PMON_CTR3 BC+B8 32x2 HA n PMON Counter 3
HAn_PCI_PMON_CTR2 B4+B0 32x2 HA n PMON Counter 2
HAn_PCI_PMON_CTR1 AC+A8 32x2 HA n PMON Counter 1
HAn_PCI_PMON_CTR0 A4+A0 32x2 HA n PMON Counter 0
Box-Level Filter
HAn_PCI_PMON_BOX_OPCODEMATCH 48 32 HA n PMON Opcode Match
HAn_PCI_PMON_BOX_ADDRMATCH1 44 32 HA n PMON Address Match 1
HAn_PCI_PMON_BOX_ADDRMATCH0 40 32 HA n PMON Address Match 0