Uncore Manual

Uncore Performance Monitoring
Memory Controller (iMC) Performance Monitoring
76 Reference Number: 329468-002
regular and special buffers at the same time. One can filter based on the memory controller chan-
nel. One or more channels can be tracked at a given time.
2.5 MEMORY CONTROLLER (IMC) PERFORMANCE MONITORING
2.5.1 Overview of the iMC
The integrated Memory Controller provides the interface to DRAM and communicates to the rest of the
uncore through the Home Agent (i.e. the iMC does not connect to the Ring).
In conjunction with the HA, the memory controller also provides a variety of RAS features, such as ECC,
lockstep, memory access retry, memory scrubbing, thermal throttling, mirroring, and rank sparing.
2.5.2 Functional Overview
The memory controller is the interface between the home Home Agent (HA) and DRAM, translating
read and write commands into specific memory commands and schedules them with respect to
memory timing. The other main function of the memory controller is advanced ECC support.
Because of the data path affinity to the HA data path, the HA is paired with the memory controller.
The uncore of Ivy Bridge-EP microarchitecture can support up to four channels of DDR3 or metaRAM.
For DDR3, the number of DIMMs per channel depends on the speed it is running and the package.
• Three or four DDR3 memory channels
• DIMM technologies supported
- UDIMM DDR3 - SR - x8 and x16 data widths; DR - x8, data width
- RDIMM DDR3 - SR, DR and QR - x4 and x8 data widths
- LRDIMM DDR3 - QR; x4 and x8 data width with direct map or with rank multiplication
• DRAM speeds supported - 800, 1067, 1333, 1600 and 1867 MT/s
• Supports up to maximum of eight ranks per channel
• Supports ECC RDIMM and LRDIMM and both ECC and non-ECC UDIMMS
• Processors supporting 4 memory channels pair channel 0 & 1 and channel 2 & 3 for lockstep
mode; otherwise the processor pairs channels 2 & 3 only.
• Processor supporting 4 memory channels also support channel 0 & 1 mirroring as well as channel
2 & 3 mirroring; otherwise the processor only supports channels 2 & 3 mirroring.
• Support for unbuffered DDR3 and registered DDR3
• Up to four independent DDR3 channels
Table 2-70. Unit Masks for WPQ_CYCLES_NO_REG_CREDITS
Extension
umask
[15:8]
Description
CHN0 b00000001 Channel 0
Filter for memory controller channel 0 only.
CHN1 b00000010 Channel 1
Filter for memory controller channel 1 only.
CHN2 b00000100 Channel 2
Filter for memory controller channel 2 only.
CHN3 b00001000 Channel 3
Filter for memory controller channel 3 only.