Uncore Manual

Reference Number: 329468-002 77
Uncore Performance Monitoring
Memory Controller (iMC) Performance Monitoring
• Eight independent banks per rank
• Support for DDR3 frequencies of 800,1067, 1333, 1600 GT/s. The speed achievable is
dependent on the number of DIMMs per channel.
• Up to three DIMMs per channel (depends on the speed)
• Support for 512 Mb, 1Gb, 2Gb, and 4Gb DIMMs
• Support for x4, x8 and x16 data lines per native DDR3 device
• ECC support (correct any error within a x4 device)
• Lockstep support for x8 chipfail
• Open or closed page policy
• Channel Mirroring per socket
• Demand and Patrol Scrubbing support
• Memory Initialization
• Poisoning Support
• Support for LR-DIMMs (load reduced) for a buffered memory solution demanding higher
capacity memory subsytems.
• Support for low voltage DDR3 (LV-DDR3, 1.35V)
2.5.3 iMC Performance Monitoring Overview
The iMC supports event monitoring through four 48-bit wide counters
(MC_CHy_PCI_PMON_CTR{3:0}) and one fixed counter (MC_CHy_PCI_PMON_FIXED_CTR) for each
DRAM channel (of which there are 4) the MC is attached to. Each of these counters can be
programmed (MC_CHy_PCI_PMON_CTL{3:0}) to capture any MC event. The MC counters will incre-
ment by a maximum of 8b per cycle.
For information on how to setup a monitoring session, refer to Section 2.1, “Uncore Per-Socket
Performance Monitoring Control”.
2.5.3.1 iMC PMON Registers - On Overflow and the Consequences (PMI/Freeze)
If an overflow is detected from an MC performance counter enabled to communicate its overflow
(MC_CHy_PCI_PMON_CTL.ov_en is set to 1), the overflow bit is set at the box level
(MC_CHy_PCI_PMON_BOX_STATUS.ov) and an overflow message is sent to the UBox. When the
UBox receives the overflow signal, the U_MSR_PMON_GLOBAL_STATUS.ov_m bit overflow is set (see
Table 2-3, “U_MSR_PMON_GLOBAL_STATUS Register – Field Definitions”) and a PMI can be gener-
ated.
Once a freeze has occurred, in order to see a new freeze, the overflow field responsible for the freeze,
must be cleared by setting the corresponding bit in MC_PCI_PMON_BOX_STATUS.ov and
U_MSR_PMON_GLOBAL_STATU.ov_m. Assuming all the counters have been locally enabled (.en bit in
data registers meant to monitor events) and the overflow bit(s) has been cleared, the iMC is prepared
for a new sample interval. Once the global controls have been re-enabled (Section 2.1.4, “Enabling a
New Sample Interval from Frozen Counters”), counting will resume.