Uncore Manual

Uncore Performance Monitoring
Memory Controller (iMC) Performance Monitoring
78 Reference Number: 329468-002
2.5.4 iMC Performance Monitors
Table 2-71. iMC Performance Monitoring MSRs
2.5.4.1 MC Box Level PMON State
The following registers represent the state governing all box-level PMUs in the MC Boxes.
In the case of the MC, the MC_CHy_PCI_PMON_BOX_CTL register provides the ability to manually
freeze the counters in the box (.frz) and reset the generic state (.rst_ctrs and .rst_ctrl).
If an overflow is detected from one of the MC Box PMON registers, the corresponding bit in the
MC_CHy_PCI_PMON_BOX_STATUS.ov field will be set. To reset these overflow bits, a user must write a
value of ‘1’ to them (which will clear the bits).
Register Name
PCICFG
Address
Size
(bits)
Description
PCICFG Base Address Dev:Func
MC0 Channel 0 PMON Registers D16:F4
MC0 Channel 1 PMON Registers D16:F5
MC0 Channel 2 PMON Registers D16:F0
MC0 Channel 3 PMON Registers D16:F1
MC1 Channel 0 PMON Registers D30:F4
MC1 Channel 1 PMON Registers D30:F5
MC1 Channel 2 PMON Registers D30:F0
MC1 Channel 3 PMON Registers D30:F1
Box-Level Control/Status
MC_CHy_PCI_PMON_BOX_STATUS F8 32 MC Channel y PMON Box-Wide Status
MC_CHy_PCI_PMON_BOX_CTL F4 32 MC Channel y PMON Box-Wide Control
Generic Counter Control
MC_CHy_PCI_PMON_FIXED_CTL F0 32 MC Channel y PMON Control for Fixed
Counter
MC_CHy_PCI_PMON_CTL3 E4 32 MC Channel y PMON Control for Counter 3
MC_CHy_PCI_PMON_CTL2 E0 32 MC Channel y PMON Control for Counter 2
MC_CHy_PCI_PMON_CTL1 DC 32 MC Channel y PMON Control for Counter 1
MC_CHy_PCI_PMON_CTL0 D8 32 MC Channel y PMON Control for Counter 0
Generic Counters
MC_CHy_PCI_PMON_FIXED_CTR D4+D0 32x2 MC Channel y PMON Fixed Counter
MC_CHy_PCI_PMON_CTR3 BC+B8 32x2 MC Channel y PMON Counter 3
MC_CHy_PCI_PMON_CTR2 B4+B0 32x2 MC Channel y PMON Counter 2
MC_CHy_PCI_PMON_CTR1 AC+A8 32x2 MC Channel y PMON Counter 1
MC_CHy_PCI_PMON_CTR0 A4+A0 32x2 MC Channel y PMON Counter 0