Uncore Manual

Uncore Performance Monitoring
Memory Controller (iMC) Performance Monitoring
80 Reference Number: 329468-002
Table 2-74. MC_CHy_PCI_PMON_CTL{3-0} Register – Field Definitions
All MC performance monitor data registers are 48-bit wide. A counter overflow occurs when a carry out
from bit 47 is detected. Software can force all uncore counting to freeze after N events by preloading a
monitor with a count value of 2
48
- N and setting the control register to send an overflow message to
the UBox (refer to Section 2.1.1, “Counter Overflow”). During the interval of time between overflow
and global disable, the counter value will wrap and continue to collect events.
If accessible, software can continuously read the data registers without disabling event collection.
This is a counter that always tracks the number of DRAM clocks (dclks - half of DDR speed) in the iMC.
The dclk never changes frequency (on a given system), and therefore is a good measure of wall clock
(unlike the Uncore clock which can change frequency based on system load). This clock is generally a
bit slower than the uclk (~800MHz to ~1.066GHz) and therefore has less fidelity.
Field Bits Attr
HW
Reset
Val
Description
thresh 31:24 RW-V 0 Threshold used in counter comparison.
rsv 23 RV 0 Reserved. SW must write to 0 else behavior is undefined.
en 22 RW-V 0 Local Counter Enable.
rsv 21 RV 0 Reserved. SW must write to 0 else behavior is undefined.
ov_en 20 RW-V 0 When this bit is asserted and the corresponding counter
overflows, its overflow bit is set in the local status register
(MC_CHy_PCI_PMON_BOX_STATUS.ov) and an overflow is
sent on the message channel to the UBox. When the
overflow is received by the UBox, the bit corresponding to
this MC will be set in
U_MSR_PMON_GLOBAL_STATUS.ov_m{1,0}.
ig 19 RV 0 Ignored
edge_det 18 RW-V 0 When set to 1, rather than measuring the event in each
cycle it is active, the corresponding counter will increment
when a 0 to 1 transition (i.e. rising edge) is detected.
When 0, the counter will increment in each cycle that the
event is asserted.
NOTE: .edge_det is in series following .thresh. Due to this,
the .thresh field must be set to a non-0 value. For events
that increment by no more than 1 per cycle, set .thresh to
0x1.
rst 17 WO 0 When set to 1, the corresponding counter will be cleared to
0.
rsv 16 RV 0 Reserved. SW must write to 0 else behavior is undefined.
umask 15:8 RW-V 0 Select subevents to be counted within the selected event.
ev_sel 7:0 RW-V 0 Select event to be counted.