Uncore Manual

Reference Number: 329468-002 81
Uncore Performance Monitoring
Memory Controller (iMC) Performance Monitoring
Table 2-75. MC_CHy_PCI_PMON_FIXED_CTL Register – Field Definitions
Table 2-76. MC_CHy_PCI_PMON_CTR{FIXED,3-0} Register – Field Definitions
2.5.5 iMC Performance Monitoring Events
2.5.5.1 An Overview:
A sampling of events available for monitoring in the iMC:
• Translated commands: Various Read and Write CAS commands
• Memory commands: CAS, Precharge, Refresh, Preemptions, etc,
• Page hits and page misses.
• Page Closing Events
• Control of power consumption: Thermal Throttling by Rank, Time spent in CKE ON mode,
etc.
and many more.
Internal iMC Queues:
RPQ - Read Pending Queue. NOTE: HA also tracks some information related to the iMC’s RPQ.
WPQ - Write Pending Queue. NOTE: HA also tracks some information related to the iMC’s WPQ.
2.5.6 iMC Box Events Ordered By Code
The following table summarizes the directly measured iMC Box events.
Field Bits Attr
HW
Reset
Val
Description
ig 31:24 RV 0 Ignored
rsv 23 RV 0 Reserved. SW must write to 0 else behavior is undefined.
en 22 RW-V 0 Local Counter Enable.
rsv 21 RV 0 Reserved. SW must write to 0 else behavior is undefined.
ov_en 20 RW-V 0 When this bit is asserted and the corresponding counter
overflows, a PMI exception is sent to the UBox.
rst 19 WO 0 When set to 1, the corresponding counter will be cleared to
0.
ig 18:0 RV 0 Ignored
Field Bits Attr
HW
Reset
Val
Description
ig 63:48 RV 0 Ignored
event_count 47:0 RW-V 0 48-bit performance event counter