Uncore Manual

Uncore Performance Monitoring
Memory Controller (iMC) Performance Monitoring
84 Reference Number: 329468-002
2.5.8 iMC Box Performance Monitor Event List
The section enumerates performance monitoring events for the iMC Box.
ACT_COUNT
• Title: DRAM Activate Count
• Category: ACT Events
• Event Code: 0x01
• Max. Inc/Cyc:. 1, Register Restrictions: 0-3
• Definition: Counts the number of DRAM Activate commands sent on this channel. Activate com-
mands are issued to open up a page on the DRAM devices so that it can be read or written to with a
CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss pre-
charges from the number of Activates.
BYP_CMDS
• Title:
• Category: BYPASS Command Events
• Event Code: 0xa1
• Max. Inc/Cyc:. 1, Register Restrictions: 0-3
• Definition:
CAS_COUNT
• Title: DRAM RD_CAS and WR_CAS Commands.
• Category: PRE Events
• Event Code: 0x04
• Max. Inc/Cyc:. 1, Register Restrictions: 0-3
• Definition: DRAM RD_CAS and WR_CAS Commands
Table 2-77. Unit Masks for ACT_COUNT
Extension
umask
[15:8]
Description
RD bxxxxxxx1 Activate due to Read
WR bxxxxxx1x Activate due to Write
BYP bxxxx1xxx Activate due to Write
Table 2-78. Unit Masks for BYP_CMDS
Extension
umask
[15:8]
Description
ACT bxxxxxxx1 ACT command issued by 2 cycle bypass
CAS bxxxxxx1x CAS command issued by 2 cycle bypass
PRE bxxxxx1xx PRE command issued by 2 cycle bypass