Uncore Manual

Uncore Performance Monitoring
Memory Controller (iMC) Performance Monitoring
86 Reference Number: 329468-002
ECC_CORRECTABLE_ERRORS
• Title: ECC Correctable Errors
• Category: ECC Events
• Event Code: 0x09
• Max. Inc/Cyc:. 1, Register Restrictions: 0-3
• Definition: Counts the number of ECC errors detected and corrected by the iMC on this channel.
This counter is only useful with ECC DRAM devices. This count will increment one time for each cor-
rection regardless of the number of bits corrected. The iMC can correct up to 4 bit errors in indepen-
dent channel mode and 8 bit errors in lockstep mode.
MAJOR_MODES
• Title: Cycles in a Major Mode
• Category: MAJOR_MODES Events
• Event Code: 0x07
• Max. Inc/Cyc:. 1, Register Restrictions: 0-3
• Definition: Counts the total number of cycles spent in a major mode (selected by a filter) on the
given channel. Major modes are channel-wide, and not a per-rank (or DIMM or bank) mode.
POWER_CHANNEL_DLLOFF
• Title: Channel DLLOFF Cycles
• Category: POWER Events
• Event Code: 0x84
• Max. Inc/Cyc:. 1, Register Restrictions: 0-3
• Definition: Number of cycles when all the ranks in the channel are in CKE Slow (DLLOFF) mode.
• NOTE: IBT = Input Buffer Termination = Off
Table 2-80. Unit Masks for DRAM_REFRESH
Extension
umask
[15:8]
Description
PANIC bxxxxxx1x
HIGH bxxxxx1xx
Table 2-81. Unit Masks for MAJOR_MODES
Extension
umask
[15:8]
Description
READ bxxxxxxx1 Read Major Mode
Read Major Mode is the default mode for the iMC, as reads are
generally more critical to forward progress than writes.
WRITE bxxxxxx1x Write Major Mode
This mode is triggered when the WPQ hits high occupancy and
causes writes to be higher priority than reads. This can cause
blips in the available read bandwidth in the system and
temporarily increase read latencies in order to achieve better
bus utilizations and higher bandwidth.
PARTIAL bxxxxx1xx Partial Major Mode
This major mode is used to drain starved underfill reads. Regular
reads and writes are blocked and only underfill reads will be
processed.
ISOCH bxxxx1xxx Isoch Major Mode
We group these two modes together so that we can use four
counters to track each of the major modes at one time. These
major modes are used whenever there is an ISOCH txn in the
memory controller. In these mode, only ISOCH transactions are
processed.