R Intel® 820E Chipset Design Guide May 2001 Document Number: 298187-003
Intel® 820E Chipset R Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document.
Intel® 820E Chipset R Contents 1. Introduction ................................................................................................................................ 13 1.1. 1.2. 1.3. 1.4. 2. Layout/Routing Guidelines ......................................................................................................... 27 2.1. 2.2. 2.3. 2.4. 2.5. 2.6. 2.7. 2.8. Design Guide About This Design Guide ..........................................................................................
Intel® 820E Chipset R 2.8.3. 2.8.4. 2.8.5. 2.8.6. 2.9. 2.10. 2.11. 2.12. 2.13. 2.14. 2.15. 2.16. 2.17. 2.18. 2.19. 2.20. 2.21. 4 2×/4× Timing Domain Routing Guidelines ...................................................62 AGP 2.0 Routing Summary .........................................................................64 AGP Clock Routing......................................................................................65 General AGP Routing Guidelines ...........................................
Intel® 820E Chipset R 2.22. 2.23. 2.24. 2.25. 3. Advanced System Bus Design................................................................................................. 139 3.1. 3.2. Design Guide LAN Layout Guidelines ................................................................................................ 102 2.22.1. ICH2 – LAN Interconnect Guidelines ........................................................ 103 2.22.1.1. Bus Topologies ......................................................
Intel® 820E Chipset R 3.2.3. 3.3. 3.4. 3.5. 3.6. 4. Clocking....................................................................................................................................163 4.1. 4.2. 4.3. 4.4. 4.5. 4.6. 4.7. 6 Pre-Layout Simulation................................................................................145 3.2.3.1. Methodology..................................................................................145 3.2.3.2. Sensitivity Analysis .............................
Intel® 820E Chipset R 4.8. 4.9. 5. System Manufacturing ............................................................................................................. 177 5.1. 6. Decoupling Recommendation for CK133 and DRCG ................................................. 174 DRCG Frequency Selection and the DRCG+ ............................................................. 175 4.9.1. DRCG Frequency Selection Table and Jitter Specification....................... 175 4.9.2.
Intel® 820E Chipset R Figures Figure 1. Intel® 820E Chipset Platform Performance Desktop Block Diagram ........................18 Figure 2. Intel® 820E Chipset Platform Performance Desktop Block Diagram (with ISA Bridge)........................................................................................................18 Figure 3. Intel® 820E Chipset Platform Dual-Processor Performance Desktop Block Diagram ................................................................................................
Intel® 820E Chipset R Figure 47. Device-Side IDE Cable Detection ........................................................................... 82 Figure 48. Connection Requirements for Primary IDE Connector ........................................... 83 Figure 49. Connection Requirements for Secondary IDE Connector ...................................... 84 Figure 50. ICH2 AC’97– Codec Connection ............................................................................ 85 Figure 51.
Intel® 820E Chipset R Figure 100. 4.5 mil Stack-Up ..................................................................................................181 Figure 101. Intel® 820E Chipset Power Delivery Example......................................................184 Figure 102. 1.8 V and 2.5 V Power Sequencing (Schottky Diode) .........................................187 Figure 103. Example 1.8V/3.3V Power Sequencing Circuit ...................................................189 Figure 104. Example 3.
Intel® 820E Chipset R Table 45. USB........................................................................................................................ 134 Table 46. LAN Connect I/F..................................................................................................... 135 Table 47. AC’97 ..................................................................................................................... 136 Table 48. ICH2 Decoupling ........................................................
Intel® 820E Chipset R Revision History Rev.
Intel® 820E Chipset R 1. Introduction The Intel® 820E Chipset Design Guide provides design recommendations for systems using the Intel® 820E chipset. This includes motherboard layout, routing guidelines, system design issues, system requirements, debug recommendations, and board schematics. In addition to providing motherboard design recommendations (e.g., layout and routing guidelines), this document also addresses system design issues such as thermal requirements for Intel 820E chipset-based systems.
Intel® 820E Chipset R 1.2. Reference Documents • Intel® 820 Chipset Family: 82820 Memory Controller Hub (MCH) Datasheet (document number: 290630) http://developer.intel.com/design/chipsets/datashts/290630.htm • Intel® 820 Chipset Design Guide Addendum for the Intel® Pentium® III Processor for the PGA370 Socket (document number 298718) http://developer.intel.com/design/chipsets/designex/298178.htm • Intel® 82802AB/82802AC Firmware Hub (FWH) Datasheet (document number: 290658) http://developer.intel.
Intel® 820E Chipset R 1.3. System Overview The Intel 820E chipset is designed for Intel® Pentium® III microprocessors and is the first chipset to support the integrated LAN capability and expanded USB capability. It supports the 4× capability of the AGP 2.0 Interface Specification and it supports the 400 MHz Direct RDRAM* interface. The 400 MHz, 16-bit, double-clocked Direct RDRAM interface provides 1.6-GB/s access to main memory.
Intel® 820E Chipset R 1.3.1. Chipset Components The Intel 820E chipset consists of the Intel® 82820 Memory Controller Hub (MCH) and the Intel® 82801BA I/O Controller Hub (ICH2). Additional functionality can be provided through the use of a PCI-to-ISA bridge. Memory Controller Hub (MCH) The MCH provides the interconnect between the Direct RDRAM and the system logic.
Intel® 820E Chipset R FWH Flash BIOS The FWH Flash BIOS component is a key element in providing a new security and manageability infrastructure for the PC platform. The device operates under the FWH Flash BIOS interface and protocol. The hardware features of this device include a unique Random Number Generator (RNG), register-based locking, and hardware-based locking. ISA Bridge For legacy needs, ISA support is an optional feature of the Intel 820E chipset.
Intel® 820E Chipset R 1.3.3. System Configuration The following figures show typical platform configurations using the Intel 820E chipset: Figure 1. Intel® 820E Chipset Platform Performance Desktop Block Diagram Intel® Pentium® III Processor Intel® 820E Chipset 4x AGP Graphics Controller AGP 2.0 Main Memory (Direct RDRAM*) Intel® 82820 Controller Hub M (MCH) Hub Interface 4 IDE Drives UltraATA/100/66/33 PCI Slots PCI Bus 4 USB Ports; 2 HC AC'97 Codec(s) (optional) AC'97 2.
Intel® 820E Chipset R Figure 3. Intel® 820E Chipset Platform Dual-Processor Performance Desktop Block Diagram Intel ® Pentium ® III Processor Intel® Pentium ® III Processor Intel ® 820E Chipset ® 4x AGP Graphics Controller AGP 2.0 Intel 82820 Memory Controller Hub (MCH) Main Memory (Direct RDRAM*) Hub Interface 4 IDE Drives UltraATA/100/66/33 PCI Slots PCI Bus 4 USB Ports; 2 HC AC'97 Codec(s) (optional) AC'97 2.
Intel® 820E Chipset R 1.4. Platform Initiatives 1.4.1. Direct Rambus RAM (RDRAM*) The Direct Rambus RAM (RDRAM) initiative provides the memory bandwidth necessary to obtain optimal performance from the Pentium III processor as well as a high-performance AGP graphics controller. The MCH RDRAM interface supports 266 MHz, 300 MHz, 356 MHz, and 400 MHz operation. The latter delivers 1.6 GB/s of theoretical memory bandwidth, which is twice the memory bandwidth of 100 MHz SDRAM systems.
Intel® 820E Chipset R 1.4.5. Integrated LAN Controller The ICH2 component incorporates an integrated LAN Controller. Its bus master capabilities enable the component to process high-level commands and perform multiple operations, which lowers processor utilization by off-loading communication tasks from the processor. The ICH2 functions with several options of LAN connect components, allowing the targeting of the desired market segment.
Intel® 820E Chipset R Function Disable The ICH2 provides the ability to disable the following functions: AC’97 Modem, AC’97 Audio, IDE, USB or SMBus. Once disabled, these functions no longer decode I/O, memory or PCI configuration space. Also, no interrupts or power management events are generated by the disabled functions. Intruder Detect The ICH2 provides an input signal (INTRUDER#) that can be attached to a switch that is activated when the system case is opened.
Intel® 820E Chipset R 1.4.9. AC’97 The Audio Codec ’97 (AC’97) specification defines a digital interface that can be used to attach an audio codec (AC), a modem codec (MC), an audio/modem codec (AMC) or both an AC and an MC. The AC’97 specification defines the interface between the system logic and the audio or modem codec, known as the AC’97 Digital Link.
Intel® 820E Chipset R Figure 4. (A-C) AC’97 Connections 4A. AC'97 with Audio Codecs (4-Channel Secondary) ICH2 360 EBGA AC’97 Digital Link AC’97 Audio Codec Audio Port AC’97 Audio Codec Audio Port 4B. AC'97 with Modem and Audio Codecs ICH2 360 EBGA AC’97 Digital Link Modem Port AC’97 Modem Codec AC’97 Audio/ Codec Audio Port 4C.
Intel® 820E Chipset R 1.4.10. Low-Pin-Count (LPC) Interface In the Intel 820E chipset platform, the super I/O component has migrated to the Low-Pin-Count (LPC) interface. Migration to the LPC interface enables lower-cost super I/O designs. The LPC super I/O component requires the same feature set as traditional super I/O components. It should include a keyboard and mouse controller, floppy disk controller, and serial and parallel ports.
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Intel® 820E Chipset R 2. Layout/Routing Guidelines This chapter documents the motherboard layout and routing guidelines for Intel 820E chipset-based systems. This chapter does not discuss the functional aspects of any bus or the layout guidelines for an add-in device. Caution: 2.1. If the guidelines in this document are not followed, it is very important to complete thorough signal integrity and timing simulations for each design.
Intel® 820E Chipset R Figure 5. MCH 324-Ball µBGA* CSP Quadrant Layout (Top View) Pin 1 System bus AGP 2.0 System bus MCH Hub interface (324-Ball µBGA* CSP) Direct RDRAM* mch_quad Figure 6.
Intel® 820E Chipset R Intel® 820E Chipset Component Placement 2.3. Notes: 1. The ATX and NLX placements and layouts shown in the following figure are recommended for single (UP) Intel 820E chipset-based system design. 2. The trace length limitation between critical connections will be discussed later in this document. 3. The figure is for reference only. Figure 7. Sample ATX and NLX MCH/ICH2 Component Placement a. Sample ATX MCH/ICH2 Component Placement CPU Host Bus MCH AGP 2.
Intel® 820E Chipset R 2.4. Core Chipset Routing Recommendations The following two figures show MCH core routing examples: Figure 8.
Intel® 820E Chipset R Figure 9.
Intel® 820E Chipset R 2.5. Source-Synchronous Strobing A technology used in AGP 4×, Direct RDRAM and the hub interface, source-synchronous strobing allows very high data transfer rates. As buses become faster and cycle times become shorter, the propagation delay becomes a limiting factor in the bus speed. Source-synchronous strobing is used to minimize the effect of propagation delay (TPROP) on maximum bus frequency.
Intel® 820E Chipset R Table 2. AGP 2× Data/Strobe Association Data Associated Strobe AD[15:0] and C/BE[1:0]# AD_STB0 AD[31:16] and C/BE[3:2]# AD_STB1 SBA[7:0] SB_STB In this example, the lower address signals (AD[15:0]) are sampled on the rising and falling edges of AD_STB0, while the upper address signals (AD[31:16]) are sampled on the rising and falling edges of AD_STB1. When routing strobes and their associated data lines, trace length mismatch is very important, in addition to noise immunity.
Intel® 820E Chipset R Because of the tolerances of components such as PCBs, connectors, and termination resistors, there will be some reflected voltage on the interconnect. In this multi-symbol interconnect, timings are pattern dependent because the reflections interfere with the next transfer. Additionally, coupled noise can greatly affect the performance of high-speed interfaces.
Intel® 820E Chipset R 2.7.2.1. RSL Routing The RSL signals enter the first RIMM on the left side, propagate through the RIMM, and exit on the right. The signal continues through the rest of the existing RIMMs until it is terminated at VTERM. All unpopulated slots must have continuity modules in place to ensure that the signals propagate to the termination. Figure 13. RSL Routing Dimensions RIMM_0 RIMM_1 MCH 0"-3.50" 0.4"-0.
Intel® 820E Chipset R The following figure shows a top view of the trace width/spacing requirements for the RSL signals. Figure 14. RSL Routing Diagram 18 mils 6 mils RSL Signal Trace Space 10 mils 6 mils Space 18 mils 6 mils Ground RSL Signal Trace Space 10 mils 6 mils Space Ground rsl_route_dia The following two figures show the top view of an example RSL breakout and route. Figure 15.
Intel® 820E Chipset R Figure 16.
Intel® 820E Chipset R 2.7.2.2. RSL Termination All RSL signals must be terminated to 1.8 V (VTERM) using 27-Ω 1% or 28 Ω 2% resistors at the end of the channel opposite the MCH. Resistor packs are acceptable. VTERM must be decoupled using highspeed bypass capacitors—one 0.1 µF ceramic chip capacitor per two RSL lines—near the terminating resistors. Additionally, bulk capacitance is required.
Intel® 820E Chipset R Figure 18. Direct RDRAM* Termination Example 2.7.2.3. Direct RDRAM* Ground Plane Reference All RSL signals must be referenced to GND to provide the optimal current return path. The Direct RDRAM ground plane reference must be continuous to the VTERM capacitors. The ground reference island under the RSL signals must be continuous from the last RIMM to the back of the termination capacitors. Choose a reference island shape that does not compromise power delivery to the components.
Intel® 820E Chipset R Figure 19. Incorrect Direct RDRAM* Ground Plane Referencing Wrong MCH 3.3-V Plane 1.8-V Plane RIMM1 RIMM2 dir_Rambus_gnd_plane_ref_incorrect Figure 20. Direct RDRAM* Ground Plane Reference MCH GND Plane Required 1.8-V Plane 3.
Intel® 820E Chipset R All four layers of the motherboard require correct grounding between the RSL signals on the motherboard, as follows: • Layer 1 = Ground isolation • Layer 2 = Ground plane • Layer 3 = Ground reference in the power plane • Layer 4 = Ground isolation All ground vias and pins MUST be connected to all 4 layers. 2.7.2.4. Direct RDRAM* Connector Compensation The RIMM connector inductance causes an impedance discontinuity on the Direct RDRAM channel.
Intel® 820E Chipset R Table 4. Copper Tab Area Calculation Dielectric Separation between Signal Trace and Thickness Copper Tab (D) 4.5 6 Min. Ground Flood Air Gap between Signal and GND Flood Compensating Capacitance (pF) Copper Tab (C-TAB) Area (A) (sq. mils) C-TAB Shape (mils) 10 6 0.65 2800 140 L x 20 W 70 L x 40 W Based on Equation 1, the tab area is 2800 sq. mils, where εr is 4.2 and D is 4.5. These values are based on 2116 prepreg material.
Intel® 820E Chipset R Figure 21.
Intel® 820E Chipset R Figure 22. Section A (See Note), Top Layer Note: 44 Refer to Figure 21. For clarity, the ground flood was removed from the picture.
Intel® 820E Chipset R Figure 23. Section A (See Note), Bottom Layer Note: Design Guide Refer to Figure 21. For clarity, the ground flood was removed from the picture.
Intel® 820E Chipset R Figure 24. Section B (See Note), Top Layer Note: 46 Refer to Figure 21. For clarity, the ground flood was removed from the picture.
Intel® 820E Chipset R Figure 25. Section B (See Note), Bottom Layer Note: Refer to Figure 21. For clarity, the ground flood was removed from the picture. 2.7.2.4.1. Direct RDRAM* Channel Connector Compensation Enhancement Recommendation From further analysis, it was determined that the amount of capacitance needed for RSL traces depends on the lengths that the signals have to travel though the RIMM connector pin. (i.e.
Intel® 820E Chipset R The copper tab area for the recommended stack-up was determined by means of simulation. The amount of capacitance required is determined by the layer on which the RSL or clocking signal is routed. The copper tabs can be placed on any signal layer, independently of the layer on which the RSL signal is routed. The following example calculation uses Equation 1. Approximate Copper Tab Area Calculation for a board with an εr of 4.2 and a prepreg thickness of 4.5 mils.
Intel® 820E Chipset R The CTAB can be implemented on the multiple layers to minimize routing and space constraints. Figure 28 shows the use of CTABs on the top and bottom layer for bottom-layer RSL and clocking signals routed between RIMMs. Figure 28. Bottom-Layer CTABs Split across the Top and Bottom Layer to Achieve an Effect CEFF ~1.35 pF 2.7.2.5. RSL Signal Layer Alternation RSL signals must alternate layers as they are routed through the channel.
Intel® 820E Chipset R Figure 29. RSL Signal Layer Alternation Signal B Signal on secondary side Signal on primary side Signal A Signal A Route on EITHER layer. Ground isolation is REQUIRED! MCH Term Signal B rsl_sig-lay_alter.vsd Table 7. RSL Routing Layer Requirements 2.7.2.6.
Intel® 820E Chipset R All RSL signals must satisfy the following equation: Equation 2. RDRAM RSL Signal Trace Length Calculation Package dimension + board trace length = Nominal RSL length ± 10 mils Figure 30.
Intel® 820E Chipset R It is necessary to compensate for the slight difference in electrical characteristics between a dummy via and a real via. Refer to the following section for more information on via compensation. 2.7.2.7. Via Compensation As described in Section 2.7.2.1, all signals must have the same number of vias. As a result, each trace will have one via (near the BGA pad) because some RSL signals must be routed on the bottom of the motherboard.
Intel® 820E Chipset R 1,2,3,4,5,6,7,8,9,10 Table 8. Line Matching and Via Compensation Example Signal Ball on Nominal MCH RSL Length (mils) Package Dimension (mils) Motherboard Trace Length When Routed on Bottom (i.e., Real Via) Min.
Intel® 820E Chipset R 2.7.3. Direct RDRAM* Reference Voltage The Direct RDRAM reference voltage (RAMREF) must be generated as shown in Figure 32. The RAMREF should be generated from a typical resistor divider using 2%-tolerance resistors. Additionally, the RAMREF must be decoupled locally at each RIMM connector, at the resistor divider, and at the MCH. Finally, as shown in Figure 32, a 100 Ω series resistor is required near the MCH. The RAMREF signal should be routed with a 10 mil-wide trace. Figure 32.
Intel® 820E Chipset R Figure 33. High-Speed CMOS Termination RIMM_0 RIMM_1 Vterm R1 91 Ω R2 39 Ω MCH high_spd_cmos_term 2.7.4.1. SIO Routing The SIO signal must be routed from RIMM to RIMM, as shown in Figure 34. The SIO signal requires a 2.2 kΩ to 10 kΩ terminating resistor on the SOUT pin of the last RIMM. SIO is routed with a standard 5 mil-wide, 60 Ω trace. The motherboard routing lengths for the SIO signal are the same as those for RSL signals. (See Figure 34.) Figure 34.
Intel® 820E Chipset R 2.7.4.2. Suspend-to-RAM Shunt Transistor When an Intel 820E chipset system enters or exits Suspend to RAM, power will be ramping to the MCH (i.e., it will be powering up or powering down). While power is ramping, the states of the MCH outputs are not guaranteed. Therefore, the MCH could drive the CMOS signals and issue CMOS commands. One of the commandsthe only one the RDRAMs will respond tois the power-down exit command.
Intel® 820E Chipset R 2.7.5. Direct RDRAM* Clock Routing Refer to Chapter 4 Clocking for the Intel 820E chipset platform’s Direct RDRAM clock routing guidelines. 2.7.6. Direct RDRAM* Design Checklist Use the following checklist as a final check to ensure that the motherboard incorporates solid design practices. This list is only a reference. For correct operation, all of the design guidelines within this document must be followed. Table 9.
Intel® 820E Chipset R If any RSL signals are routed, even for a short distance, out of the last RIMM (towards termination) on the bottom side, ensure that the ground reference plane (on the third layer) is continuous under the termination resistors/capacitors. Ensure that the current path for power delivery to the MCH does not go through the VTERM island. • CTM/CTM# routed properly CTM/CTM# are routed differentially from DRCG to last RIMM. CTM/CTM# are ground-isolated from DRCG to last RIMM.
Intel® 820E Chipset R All RSL signals are routed adjacent to a ground reference plane. This includes all signals from the last RIMM to the termination. If signals are routed on the bottom from the last RIMM to the termination, the ground reference plane on the 3rd layer must extend under these signals and include the ground side of the VTERM decoupling capacitors. CTABs must not cross (or be on top of) power plane splits. They must be entirely referenced to ground.
Intel® 820E Chipset R 2.8. AGP 2.0 For detailed AGP interface functionality (e.g., protocols, rules, signaling mechanisms), refer to Revision 2.0 of the latest AGP Interface Specification obtainable from http://www.agpforum.org. This document focuses only on specific Intel 820E chipset platform recommendations. Revision 2.0 of the AGP Interface Specification enhances the functionality of the original AGP Interface Specification (Rev. 1.0) by allowing 4× data transfers (4 data samples per clock) and 1.
Intel® 820E Chipset R Signal Groups • 1× timing domain CLK (3.
Intel® 820E Chipset R Table 10. AGP 2.0 Data/Strobe Associations Data Associated Strobe in 1× Associated Strobe in 2× Associated Strobes in 4× AD[15:0] and C/BE[1:0]# Strobes are not used in 1× mode. All data is sampled on rising clock edges. AD_STB0 AD_STB0, AD_STB0# AD[31:16] and C/BE[3:2]# Strobes are not used in 1× mode. All data is sampled on rising clock edges. AD_STB1 AD_STB1, AD_STB1# SBA[7:0] Strobes are not used in 1× mode. All data is sampled on rising clock edges.
Intel® 820E Chipset R 5.8 inches long. Another strobe set (e.g., SB_STB and SB_STB#) could be 4.2 inches long, and the data signals associated with those strobe signals (e.g., SBA[7:0]) can be 3.7 inches to 4.7 inches long. The strobe signals (AD_STB0, AD_STB0#, AD_STB1, AD_STB1#, SB_STB, and SB_STB#) act as clocks on the source-synchronous AGP interface. Therefore, special care must be taken when routing these signals.
Intel® 820E Chipset R The strobe signals (AD_STB0, AD_STB0#, AD_STB1, AD_STB1#, SB_STB, and SB_STB#) act as clocks on the source-synchronous AGP interface. Therefore, special care must be taken when routing these signals. Because each strobe pair is truly a differential pair, the pair should be routed together. (For example, AD_STB0 and AD_STB0# should be routed next to each other.) The two strobes in a strobe pair should be routed on 5 mil traces with at least 20 mils of space (1:4) between them.
Intel® 820E Chipset R 2.8.5. AGP Clock Routing The maximum total AGP clock skew (between the MCH and the graphics component) is 1 ns for all data transfer modes. This 1 ns includes skew and jitter that originates on the motherboard, add-in card, and clock synthesizer. Clock skew must be evaluated not only at a single threshold voltage, but at all points on the clock edge that fall within the switching range. The 1-ns skew budget is divided such that the motherboard is allotted 0.9 ns of clock skew.
Intel® 820E Chipset R Figure 37. Top Signal Layer Ground Reference It is strongly recommended that, at a minimum, the following critical signals be referenced to ground from the MCH to an AGP connector (or to an AGP video controller, if implemented as a “down” solution), utilizing a minimum number of vias on each net: AD_STB0, AD_STB0#, AD_STB1, AD_STB1#, SB_STB, SB_STB#, G_GTRY#, G_IRDY#, G_GNT#, and ST[2:0].
Intel® 820E Chipset R Note: The motherboard provides 3.3 V to the VCC pins of the AGP connector. If the graphics controller needs a lower voltage, then the add-in card must regulate the 3.3 V VCC voltage to the controller’s requirements. The graphics controller may only power AGP I/O buffers with the VDDQ power pins. The TYPEDET# signal indicates whether the AGP 2.0 interface operates at 1.5 V or 3.3 V. If TYPEDET# is floating (i.e., no connect) on an AGP add-in card, the interface is 3.3 V.
Intel® 820E Chipset R Figure 38. AGP VDDQ Generation Example Circuit +3.3V O +12V O VDDQ O C2 47 µF U1 1 LT1575 SHDN IPOS VIN INEG GND GATE FB COMP 2 R1 1 kΩ 3 C1 1 µF 4 5 6 5Ω C3 220 µF R2 7 8 C4 10 pF C5 47 µF R5 7.5 kΩ R3 301 Ω TYPEDET# R4 1.21 kΩ agp_vddq_generation.vsd 2.8.8. VREF Generation for AGP 2.0 (2× and 4×) VREF generation for AGP 2.0 will differ, depending on the AGP card type used. The 3.3 V AGP cards generate VREF locally (i.e.
Intel® 820E Chipset R During a 3.3 V AGP 2.0 operation, VREF must be 0.4 VDDQ. However, during a 1.5 V AGP 2.0 operation, VREF must be 0.5 VDDQ. This requires a flexible voltage divider for VREF. Various methods of accomplishing this exist, such as the example in the following figure. Figure 39. AGP 2.0 VREF Generation and Distribution +12 V R7 (Note 2) 1 kΩ 1.5-V AGP Card R9 300 Ω 1% TYPEDET# VDDQ C8 500 pF R11 200 Ω 1% VrefGC U6 VDDQ REF C10 0.
Intel® 820E Chipset R 2.8.9. Compensation The MCH AGP interface supports resistive buffer compensation (RCOMP). Tie the GRCOMP pin to a 40 Ω, 2% (or 39-Ω, 1%) pull-down resistor (to ground), via a 10 mil-wide, very short (<0.5 inch) trace. 2.8.10. AGP Pull-Ups AGP control signals require pull-up resistors to VDDQ on the motherboard, to ensure that they maintain stable values when no agent is actively driving the bus.
Intel® 820E Chipset R 2.8.10.1. AGP Signal Voltage Tolerance List The following signals on the AGP interface are 3.3 V tolerant during a 1.5 V operation: • PME# • INTA# • INTB# • GPERR# • GSERR# • CLK • RST The following signals on the AGP interface are 5 V tolerant (refer to the USB specification): • USB+ • USB• OVRCNT# The following signal is a special AGP signal, which is either grounded or not connected on an AGP card. • TYPEDET# Note: 2.8.11.
Intel® 820E Chipset R 2.8.12. AGP Universal Retention Mechanism (RM) Environmental testing and field reports indicate that, without proper retention, AGP cards and AGP In-Line Memory Module (AIMM) cards may come unseated during system shipping and handling. In order to prevent the disengagement of AGP cards and AIMM modules, Intel recommends that AGPbased platforms use the AGP retention mechanism (RM).
Intel® 820E Chipset R Figure 41. AGP Left-Handed RM Keep-Out Information Recommended for all AGP cards, the AGP RM is detailed in Engineering Change Request No. 48 (ECR #48), which details approved changes to the Accelerated Graphics Port (AGP) Interface Specification, Revision 2.0. Intel intends to incorporate the AGP RM changes into later revisions of the AGP interface specification. In addition, Intel has defined a reference design for a mechanical device utilizing the features defined in ECR #48.
Intel® 820E Chipset R 2.9. Hub Interface The MCH and ICH2 ballout assignments have been optimized to simplify the hub interface routing between these devices. It is recommended that the hub interface signals be routed directly from the MCH to ICH2, with all signals referenced to VSS. Layer transition should be keep to a minimum. If a layer change is required, use only two vias per net and keep all data signals and associated strobe signals on the same layer.
Intel® 820E Chipset R 2.9.1. 8-Bit Hub Interface Routing Guidelines This section documents the routing guidelines for the 8-bit hub interface. This hub interface connects the ICH2 to the MCH. This interface supports two buffer modes: normal and enhanced. The ICH2 uses its HLCOMP pin to set the buffer mode, and the MCH uses its HLA_ENH# pin to configure its 8-bit hub interface buffers. Both devices must be configured for the same buffer mode.
Intel® 820E Chipset R Table 16. 8-Bit Hub Interface HUBREF Generation Circuit Specifications Buffer Mode HUBREF Voltage Specification (V) Recommended Resistor Values for the HUBREF Divider Circuit (Ω ) Normal/Single 1/2 VCC 1_8 ± 2% R1 = R2 = 150 ± 1% Normal/Local 2/3 VCC 1_8 ± 2% R1 = 150 ± 1%, R2 = 301 ± 1% The single HUBREF divider should not be located more than 4 inches away from either MCH or ICH2.
Intel® 820E Chipset R 2.9.1.4. 8-Bit Hub Interface Compensation The hub interface uses a compensation signal to adjust buffer characteristics to the specific board characteristic. The hub interface requires resistive compensation (RCOMP). The guidelines are as follows shown in the following table. Table 17.
Intel® 820E Chipset R 2.10.1. System Bus Ground Plane Reference All system bus signals must be referenced to GND to provide the optimal current return path. The ground reference must be continuous from the MCH to the Intel PGA370 socket. This may require a GND reference island on the plane layers closest to the signals. Any split in the ground island will provide a suboptimal return path. In a 4-layer board, this will require that the VCCID island be on an outer signal layer.
Intel® 820E Chipset R Additional Considerations • Distribute VTT with a wide trace. A 0.050 inch minimum trace is recommended to minimize DC losses. Route the VTT trace to all components on the host bus. Be sure to include decoupling capacitors. Guidelines for VTT distribution and decoupling are contained in the Intel® 820 Chipset Design Guide Addendum for the Intel® Pentium® III Processor for the PGA370 Socket.
Intel® 820E Chipset R 2.12.1. Cable Detection for Ultra ATA/66 and Ultra ATA/100 The ICH2 IDE controller supports PIO, multiword (8237-style) DMA, and Ultra DMA modes 0 through 5. The ICH2 must determine the type of cable present, to configure itself for the fastest possible transfer mode that the hardware can support. An 80-conductor IDE cable is required for Ultra ATA/66 and Ultra ATA/100. This cable uses the same 40-pin connector as the old 40-pin IDE cable.
Intel® 820E Chipset R Figure 46. Combination Host-Side/Device-Side IDE Cable Detection IDE drive IDE drive 5V 5V To secondary IDE connector GPIO ICH2 GPIO 10 kΩ 10 kΩ PDIAG# PDIAG# 40-conductor cable PDIAG#/ CBLID# 10 kΩ Resistor required for non-5V-tolerant GPI. 5V To secondary IDE connector 80-conductor GPIO ICH2 GPIO IDE drive IDE drive 5V 10 kΩ 10 kΩ PDIAG# PDIAG# IDE cable PDIAG#/ CBLID# Resistor required for non-5V-tolerant GPI.
Intel® 820E Chipset R 2.12.3. Device-Side Cable Detection For platforms that must implement device-side detection only (e.g., NLX platforms), a 0.047 µF capacitor is required on the motherboard, as shown in the following figure. This capacitor should not be populated when implementing the recommended combination host-side/device-side cable detection mechanism described previously. Figure 47.
Intel® 820E Chipset R 2.12.4. Primary IDE Connector Requirements Figure 48. Connection Requirements for Primary IDE Connector PCIRST_BUF# 22–47 Ω Reset# PCIRST# * PDD[15:0] PDA[2:0] PDCS1# PDCS3# PDIOR# PDIOW# PDDREQ 3.3 V 4.7 kΩ 3.3 V 8.2–10 kΩ Primary IDE Connector PIORDY IRQ14 PDDACK# GPIOx PDIAG# / CBLID# CSEL 10 kΩ ICH2 * Due to ringing, PCIRST# must be buffered. N.C. Pins 32 & 34 IDE_primary_conn_require NOTES: 1. 22 Ω to 47 Ω series resistors are required on RESET#.
Intel® 820E Chipset R 2.12.5. Secondary IDE Connector Requirements Figure 49. Connection Requirements for Secondary IDE Connector PCIRST_BUF# 22–47 Ω Reset# PCIRST# * SDD[15:0] SDA[2:0] SDCS1# SDCS3# SDIOR# SDIOW# SDDREQ 3.3 V 4.7 kΩ 3.3 V 8.2–10 kΩ Secondary IDE Connector SIORDY IRQ15 SDDACK# GPIOy PDIAG# / CBLID# CSEL 10 kΩ ICH2 * Due to ringing, PCIRST# must be buffered. N.C. Pins 32 & 34 IDE_secondary_conn_require NOTES: 1. 22 Ω to 47 Ω series resistors are required on RESET#.
Intel® 820E Chipset R 2.13. AC’97 The ICH2 implements an AC’97 2.1-compliant digital controller. Any codec attached to the ICH2 AC-link also must be AC’97 2.1 compliant. Please contact your codec IHV for information on 2.1-compliant products. The AC’97 2.1 specification is on the following Intel web page: http://developer.intel.com/pc-supp/platform/ac97/index.htm The AC-link is a bi-directional, serial PCM digital stream.
Intel® 820E Chipset R Clocking is provided from the primary codec on the link via BITCLK, and is derived from a 24.576 MHz crystal or oscillator. Refer to the primary codec vendor for the crystal or oscillator requirements. BITCLK is a 12.288 MHz clock driven by the primary codec to the digital controller (ICH2) and any other codec present. This clock is used as the time base for latching and driving data. The ICH2 supports Wake on Ring from S1-S5 via the AC’97 link.
Intel® 820E Chipset R Figure 51.
Intel® 820E Chipset R Figure 52. CDC_DN_ENAB# Support Circuitry for Multi-Channel Audio Upgrade Motherboard Primary Audio Codec CNR Board SDATA_IN RESET# Audio Codec From AC '97 Controller RESET# SDATA_IN AC97_RESET# ID0# Vcc RB 100 kΩ Ω To General Purpose Input To AC '97 Digital Controller CDC_DN_ENAB# RA 10 kΩ Ω SDATA_IN0 SDATA_IN1 CNR Connector Figure 52 shows the circuitry required on the motherboard to support a two-codec down configuration.
Intel® 820E Chipset R Figure 54. CDC_DN_ENAB# Support Circuitry for Two-Codecs on Motherboard / Two-Codecs on CNR Codec A Codec B SDATA_IN RESET# Motherboard CNR Board SDATA_IN RESET# Codec C RESET# From AC '97 Controller AC97_RESET# SDATA_IN Vcc Codec D To General Purpose Input To AC '97 Digital Controller RB 1 κΩ CDC_DN_ENAB# RESET# SDATA_IN RA 10 kΩ Ω SDATA_IN0 SDATA_IN1 CNR Connector Circuit Notes 1.
Intel® 820E Chipset R Valid Codec Configurations Table 19. Codec Configurations Valid Codec Configurations Invalid Codec Configurations AC(Primary) MC(Primary) + X(any other type of codec) MC(Primary) AMC(Primary) + AMC(Secondary) AMC(Primary) AMC(Primary) + MC(Secondary) AC(Primary) + MC(Secondary) AC(Primary) + AC(Secondary) AC(Primary) + AMC(Secondary) 2.13.2. Communication and Networking Riser (CNR) Related Documents: Communication Network Riser Specification, Revision 1.
Intel® 820E Chipset R 2.13.3. AC’97 Routing To ensure the maximum performance of the codec, proper component placement and routing techniques are required. These techniques include properly isolating the codec, associated audio circuitry, analog power supplies, and analog ground planes, from the rest of the motherboard. This includes plane splits and proper routing of signals not associated with the audio section. Contact your vendor for devicespecific recommendations.
Intel® 820E Chipset R 2.13.4. Motherboard Implementation The following design considerations are provided for the implementation of an ICH2 platform using AC’97. These design guidelines have been developed to ensure maximum flexibility for board designers, while reducing the risk of board-related issues. These recommendations are not the only implementation or a complete checklist, but they are based on the ICH2 platform.
Intel® 820E Chipset R Figure 56. USB Data Signals P+ Motherboard Trace 15 Ω < 1" 45 Ω 15k Driver P- Optional 47 pF Motherboard Trace 15 Ω < 1" 45 Ω 15k 90 Ω Optional 47 pF Transmission Line ICH2 USB Connector Driver USB Twisted Pair Cable Recommended USB trace characteristics • Impedance Z0 = 45.4 Ω • Line delay = 160.2 ps • Capacitance = 3.5 pF • Inductance = 7.3 nH • Resistance at 20 °C = 53.9 mΩ 2.14.3.
Intel® 820E Chipset R 2.16. I/O APIC Design Recommendation UP systems not using the integrated I/O APIC should comply with the following recommendations: • On the ICH2 Connect PICCLK directly to ground. Connect PICD0 and PICD1 to ground through a 10 kΩ resistor. • On the processor PICCLK must be connected from the clock generator to the PICCLK pin on the processor. Connect PICD0 to 2.5 V through 10 kΩ resistors. Connect PICD1 to 2.5 V through 10 kΩ resistors. 2.17.
Intel® 820E Chipset R Figure 57. SMBUS/SMLink Interface SPD data Host controller slave interface Network interface card on PCI Temperature on thermal sensor SMBus 82801BA ICH2 SMBCLK Microcontroller SMBDATA SMLink SMLink0 SMLink1 Wire OR (optional) Intel® 8255 Motherboard LAN controller smbus_smlink_IF Note: Intel does not support external access to the ICH2’s integrated LAN controller via the SMLink interface.
Intel® 820E Chipset R 2.18. PCI The ICH2 provides a PCI Bus interface that is compliant with the PCI Local Bus Specification, Revision 2.2. The implementation is optimized for high-performance data streaming when the ICH2 acts as either the target or the initiator on the PCI bus. For more information on the PCI Bus interface, refer to the PCI Local Bus Specification, Revision 2.2. The ICH2 supports six PCI Bus masters, excluding the ICH2, by providing six REQ#/GNT# pairs.
Intel® 820E Chipset R 2.19.1. RTC Crystal The ICH2 RTC module requires an external 32.768 kHz oscillating source connected on the RTCX1 and RTCX2 pins. The following figure shows the external circuitry that comprises the oscillator of the ICH2 RTC. Figure 59. External Circuitry for the ICH RTC 2 VCCRTC3 VCC3_3SBY 1 kΩ 1 µF RTCX24 Vbat_rtc 1 kΩ 32768 Hz Xtal R1 10 MΩ RTCX15 C1 0.047 uF C31 R2 10 MΩ VBIAS6 C21 VSS7 rtc_cir NOTES: 1.
Intel® 820E Chipset R 2.19.3. RTC Layout Considerations • Minimize the RTC lead lengths. Approximately 0.25 inch is sufficient. • Minimize the capacitance between Xin and Xout in the routing. • Put a ground plane under the XTAL components. • Do not route switching signals under the external components (unless on the other side of the board). • The oscillator VCC should be clean. Use a filter (e.g., an RC low-pass) or a ferrite inductor. 2.19.4.
Intel® 820E Chipset R A standby power supply should be used in a desktop system to provide continuous power to the RTC when available, which will significantly increase the RTC battery life and thereby increase the RTC accuracy. 2.19.5. RTC External RTCRST Circuit The ICH2 RTC requires additional external circuitry. The RTCRST# signal is used to reset the RTC well.
Intel® 820E Chipset R 2.19.6. RTC Routing Guidelines • All RTC OSC signals (RTCX1, RTCX2, VBIAS) should be routed with trace lengths of less than 1 inch. The shorter, the better. • Minimize the capacitance between RTCX1 and RTCX2 in the routing. (Optimally, there would be a ground line between them.) • Put a ground plane under all external RTC circuitry. • Do not route any switching signals under the external components (unless on the other side of the ground plane). 2.19.7.
Intel® 820E Chipset R logic low. When the jumper is not populated, a low can still be read on the signal line if the effective impedance due to the speaker and codec circuit is equal to or less than that of the integrated pull-up resistor. Therefore, it is strongly recommended that the effective impedance be greater than 50 kΩ and the pull-down resistor be less than 7.3 kΩ. Figure 62. SPKR Circuit ICH2 3.3 V Integrated pull-up 18–42 kΩ SPKR Stuff jumper to disable timeout feature. R < 7.
Intel® 820E Chipset R Interrupts B, D, E, and H service devices internal to the ICH2. Interrupts A, C, F, and G are unused and can be used by PCI slots. The following figure shows an example of IRQ line routing to the PCI slots. Figure 63.
Intel® 820E Chipset R Figure 64. ICH2 / LAN Connect Section B C ® ICH2 Intel 82562EH/82562ET Dual footprint A Magnetics module Connector Refer to Intel 82562EH/82562ET section D ICH2_LAN_connect Table 22. LAN Design Guide Section Reference Layout Section ICH2 – LAN interconnect A General routing guidelines B,C,D ® 2.22.1. Previous Figure Reference Design Guide Section 2.22.1 ICH2 – LAN Interconnect Guidelines 2.22.
Intel® 820E Chipset R 2.22.1.1. Bus Topologies The LAN Connect Interface can be configured in several topologies, as follows: • Direct point-to-point connection between the ICH2 and the LAN component • Dual footprint (see Section 2.22.6.) • LOM/CNR implementation 2.22.1.2. Point-to-Point Interconnect The following are guidelines for a single-solution motherboard. Either the Intel 82562EH component, Intel 82562ET component or CNR is installed. Figure 65.
Intel® 820E Chipset R Figure 66. LOM/CNR Interconnect B PLC A Res. pack ICH2 C D CNR PLC card IO_subsys_LOM-CNR_intercomm Table 23. Length Requirements for Figure 66 Configuration A B 0.5” to 6” 4” to (10” – A) 0.5” to 7” 3” to (10” – A) Dual footprint 0.5” to 6.5” 3.5” to (10” – A) Intel® 82562ET/EH card (see Note) 0.5” to 6.5” Intel® 82562EH ® Intel 82562ET C D 2.5” to (9” – A) 0.5” to 3” Note: The total trace length should not exceed 13 inches.
Intel® 820E Chipset R Figure 67. LAN_CLK Routing Example LAN_RXD0 2.22.1.5. LAN_CLK Crosstalk Consideration Crosstalk-induced noise must be carefully minimized. Crosstalk is the principal cause of timing skews and is the largest part of the tRMATCH skew parameter. 2.22.1.6. Impedances Motherboard impedances should be controlled to minimize the effect of any mismatch between the motherboard and an add-in card. An impedance of 60 Ω ± 15% is strongly recommended.
Intel® 820E Chipset R 2.22.2. 2.22.2.1. General LAN Routing Guidelines and Considerations General Trace Routing Considerations Trace routing considerations are important to minimize the effects of crosstalk and propagation delays on board sections where high-speed signals exist. Signal traces should be kept as short as possible to decrease interference from other signals, including those propagated through the power and ground planes.
Intel® 820E Chipset R 2.22.2.1.1. Trace Geometry and Length The key factors in controlling trace EMI radiation are the trace length and the ratio of trace width to trace height above the ground plane. To minimize trace inductance, high-speed signals and signal layers close to a ground or power plane should be as short and wide as practical. Ideally, this ratio of trace width to height above ground plane should be between 1:1 and 3:1.
Intel® 820E Chipset R Figure 69. Ground Plane Separation Separate Chassis Ground Plane Good grounding requires the minimization of inductance levels in the interconnections. EMI radiation can be reduced significantly by keeping ground returns short, signal loop areas small, and power inputs bypassed to signal return. Rules that help reduce backplane and motherboard circuit inductance include the following: • Route traces over a continuous plane with no interruptions (i.e.
Intel® 820E Chipset R 2.22.2.3. 4-Layer Board Design Top-Layer Routing Sensitive analog signals are routed completely on the top layer without the use of vias. This allows tight control of signal integrity and removes any impedance inconsistencies due to layer changes. Ground Plane A layout split (100 mils) of the ground plane under the magnetics module between the primary and secondary side of the module is recommended.
Intel® 820E Chipset R should be kept at least 0.3 inch from the nearest receive trace. Possible exceptions are only where the traces enter or exit the magnetics, the RJ-45/11, and the PLC. 6. Use of an inferior magnetics module. The magnetics modules used by Intel have been fully tested for IEEE PLC conformance, for long-cable BER, and for emissions and immunity. (Inferior magnetics modules often have less common-mode rejection and/or no autotransformer in the transmit channel.) 7.
Intel® 820E Chipset R 2.22.3. Intel® 82562EH Home/PNA* Guidelines Table 24. Related Documents Title Doc # Intel® 82562EH HomePNA 1-Mbit/s Physical Layer Interface Product Preview Datasheet OR-2183 RS-82562EH 1-Mbit/s Home PNA LAN Connect Option Application Note OR-2182 For correct LAN performance, designers must follow the general guidelines outlined in Section 2.22.2. Additional guidelines for implementing an Intel 82562EH Home/PNA* LAN connect component are provided in the following sections. 2.
Intel® 820E Chipset R For noise-free and stable operation, place the crystal and associated discretes as close as possible to the Intel 82562EH component, keeping the length as short as possible. Do not route any noisy signals in this area. 2.22.3.4. Phoneline HPNA Termination The transmit/receive differential-signal pair is terminated with a pair of 51.1 Ω (1%) resistors. This parallel termination should be placed close to the Intel 82562EH component. The center, common point between the 51.
Intel® 820E Chipset R 2.22.3.5. Critical Dimensions As shown in the following figure, there are three dimensions to consider during layout: Distance B, from the line RJ11 connector to the magnetics module; distance C, from the phone RJ11 to the LPF (if implemented); and distance A, from the Intel 82562EH component to the magnetics module. Figure 71.
Intel® 820E Chipset R 2.22.3.5.3. Distance from LPF to Phone RJ11 Distance ‘C’ should be less than 1 inch. Regarding trace symmetry, route differential pairs with consistent separation and with exactly the same lengths and physical dimensions. Asymmetry and unequal length in the differential pairs contribute to common-mode noise. This can degrade the receive-circuit performance and contribute to radiated emissions from the transmit side. 2.22.4.
Intel® 820E Chipset R 2.22.4.2. Crystals and Oscillators To minimize the effects of EMI, clock sources should not be placed near I/O ports or board edges. Radiation from these devices may be coupled onto the I/O ports or out of the system chassis. Crystals also should be kept away from the Ethernet magnetics module, to prevent communication interference.
Intel® 820E Chipset R Figure 73. Critical Dimensions for Component Placement B ICH2 A Intel® 82562ET / 82562EM Magnetics Module EEPROM Line RJ45 crit_dim_comp_plac Distance Priority Guideline A 1 <1 inch B 2 <1 inch 2.22.4.4.1. Distance from Magnetics Module to RJ45 Distance ‘A,’ in the previous figure, should be given the highest priority during board layout. The separation between the magnetics module and the RJ45 connector should be kept to less than 1 inch.
Intel® 820E Chipset R ® 2.22.4.4.2. Distance from the Intel 82562ET Component to the Magnetics Module Distance ‘B’ in Figure 73 also should be designed to be less than 1 inch between devices. The high-speed nature of the signals propagating through these traces requires that the distance between these components be observed closely. Generally speaking, any trace section intended for use with high-speed signals should comply with proper termination practices.
Intel® 820E Chipset R Figure 74. Termination Plane TDP N/C TDN RDP RJ-45 RDN Magnetics Module Termination Plane Additional capacitance that may need to be added for EFT testing term_plane 2.22.5. Intel® 82562ET/EM Disable Guidelines To disable the Intel 82562ET/EM, the device must be isolated (disabled) prior to reset (RSM_PWROK) asserting. Using a GPIO, such as GPO28 to be LAN_Enable (enabled high), LAN will default to enabled on initial power-up and after an AC power loss.
Intel® 820E Chipset R There are four pins which are used to put the Intel 82562ET/EM controller in different operating states: Test_En, Isol_Tck, Isol_Ti, and Isol_Tex. The table below describes the operational/disable features for this design.
Intel® 820E Chipset R Figure 77. Dual-Footprint Analog Interface ® Intel 82562EH/82562ET Tip TDP TDN RDP Ring Magnetics module RDN RJ11 TXP RJ45 TXN Intel 82562EH config. Intel 82562ET config. IO_subsys_dual_footprint_analog_ IF Additional guidelines for this configuration are as follows: • L = 0.5 inch to 6.5 inches • Stub = <0.5 inch • Either the Intel 82562EH or Intel 82562ET/82562EM component can be installed. Not both.
Intel® 820E Chipset R • Traces from magnetics to connector must be shared and not stubbed. An RJ-11 connector that fits into the RJ-45 slot is available. Any amount of stubbing will destroy both HomePNA* and Ethernet performance. 2.22.7. ICH2 Decoupling Recommendations The ICH2 can generate large current swings when switching between logic high and logic low. This condition could cause the component voltage rails to drop below the specified limits.
Intel® 820E Chipset R Figure 78. Decoupling Capacitor Layout 3.3 V Core 1.8 V Core 1.8 V Standby 3.3 V Standby 1.8 V Standby 5 V Ref 3.3 V Core ICH2_decoupling_cap The previous figure shows the layout of the ICH2 decoupling capacitors for various power planes around the ICH2. The decoupling caps are circled, with an arrow pointing to the power plane/trace to which they are connected.
Intel® 820E Chipset R 2.23. FWH Flash BIOS Guidelines The general compatibility guidelines and the design recommendations for supporting the FWH Flash BIOS device are discussed next. Most changes will be incorporated into the BIOS. Refer to the FWH Flash BIOS specification or equivalent. 2.23.1. In-Circuit FWH Flash BIOS Programming All cycles destined for the FWH Flash BIOS appear on PCI.
Intel® 820E Chipset R 2.24. ICH2 Design Checklist This checklist highlights design considerations that should be reviewed before manufacturing an Intel 820E chipset-based motherboard that implements an ICH2. The entries in this checklist should provide the important connections to these devices and any critical supporting circuitry. This is not a complete list and it doesn’t guarantee that a design will function properly. This list is only a reference.
Intel® 820E Chipset R Table 27. Hub Interface Checklist Items Recommendations Reason/Effect HL[11] No pull-up resistor is required. Use a no-stuff or a test point to put the ICH2 into NAND chain mode testing. HL_COMP Tie the COMP pin to a 40 Ω, 1% or 2% (or 39 Ω, 1%) pull-up resistor (to 1.8 V), via a 10 mil wide, very short (~0.5 inch) trace. ZCOMP no longer supported. Table 28. LAN Interface Checklist Items Recommendations LAN_CLK Connect to platform LAN connect device.
Intel® 820E Chipset R Table 31. Interrupt Interface Checklist Items PIRQ#[D:A] PIRQ#[G:F] / GPIO[4:3] PIRQ#[H] PIRQ#[E] APIC Recommendations Reason/Effect These signals require a pull-up resistor. A 2.7 kΩ pull-up resistor to VCC 5 V or an 8.2 kΩ pull-up resistor to VCC 3.3 V is recommended. In a non-APIC mode, the PIRQx# signals can be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15. Each PIRQx# line has a separate Route Control Register. These signals require a pull-up resistor.
Intel® 820E Chipset R Table 32. GPIO Checklist Items GPIO pins Recommendations GPIO[0:7]: • These pins are in the main power well. Pull-ups must use the 3.3 V plane. Reason/Effect Ensure that all unconnected signals are outputs only! • Unused core well inputs must either be pulled up to VCC3.3 or be pulled down. These inputs must not be allowed to float. • GPIO[1:0] can be used as REQ[A:B]#. • GPIO[1] also can be used as PCI REQ[5]#. • These signals are 5 V tolerant.
Intel® 820E Chipset R Table 34. Power Management Checklist Items Recommendations Reason/Effect THRM# Connect to temperature sensor. Pull-up if not used. Input to ICH2 cannot float. THRM# polarity bit defaults THRM# to active low, so pull-up. SLP_S3# No pull-up/pull-down resistors needed. Signals driven by ICH2. Signal driven by ICH2.
Intel® 820E Chipset R Table 36. System Management Checklist Items SMBDATA SMBCLK Recommendations Reason/Effect Requires external pull-up resistors to 3.3 V or 3.3 V standby. Value of pull-up resistors is determined by the line load. Open-drain signal in resume well SMBALERT#/ GPIO[11] See GPIO section if SMBALERT# not implemented. SMLINK[1:0] Requires external pull-up resistors to 3.3 V. Open-drain signal in resume well INTRUDER# Pull signal to VBAT if not needed. Signal in VCCRTC (VBAT) well.
Intel® 820E Chipset R Table 39. Miscellaneous Signals Checklist Items SPKR Recommendations No extra pull-up resistors Effective impedance due to speaker and codec circuitry must be greater than 50 kΩ, or a means to isolate the resistive load from the signal while PWROK is low must be found. Reason/Effect Has integrated pull-up with a resistance between 18 kΩ and 42 kΩ. The integrated pullup is enabled only during boot/reset for strapping functions. At all other times, the pullup is disabled.
Intel® 820E Chipset R Figure 73. 5VREF Circuitry Vcc supply (3.3 V) 5 V supply 1 kΩ 1 µF To system To system Vref sys_des_5Vref_circ Table 41. IDE Checklist Checklist Items PDD[15:0], SDD[15:0] Recommendations Reason/Effect No extra series termination resistors or other pull-ups/pull-downs are required. These signals have integrated series resistors. • PDD7/SDD7 doesn’t require a 10 kΩ pull-down resistor.
Intel® 820E Chipset R Checklist Items Recommendations • Host Side/Device Side Detection: Cable Detect* Connect the IDE pin PDIAG/CBLID to an ICH2 GPIO pin. Connect a 10 kΩ resistor to GND on the signal line. • Device-side detection: Connect a 0.04 µF capacitor from the IDE pin PDIAG/CBLID to GND. No ICH2 connection Note: Reason/Effect The 10 kΩ resistor to GND prevents GPI from floating, if no devices are present on either IDE interface. Allows the use of 3.3 V GPIOs that are not 5 V tolerant.
Intel® 820E Chipset R 2.25. ICH2 Layout Checklist Table 43. 8-Bit Hub Interface # Layout Recommendations 1 Board impedance must be 60 Ω ± 10%. 2 Traces must be routed 5 mils wide with 20 mils spacing. 3 In order to break out of the MCH and ICH2 package, the hub interface signals can be routed 5 on 5. Signals must be separated to 5 on 20 within 300 mils of the package. 4 Max. trace length is 8 inches. 5 Data signals must be matched within ±0.1 inch of the HL_STB diff pair.
Intel® 820E Chipset R Table 46. LAN Connect I/F # Design Guide Layout Recommendations Yes No Comments 1 Stack-up: 5 mils wide, 10 mil spacing 2 Z0 = 60 Ω ± 15% Signal integrity requirement 3 LAN max. trace length, ICH2 to CNR : L = 3 inches to 9 inches (0.5 inch to 3 inches on card) To meet timing requirements 4 Stubs due to R-pak CNR/LOM stuffing option should not be present. To minimize inductance 5 Max. trace lengths, ICH2 to 82562EH/ET/EM : L = 4.5 inches to 8.
Intel® 820E Chipset R # Layout Recommendations Yes No Comments 20 Isolate I/O signals from high-speed signals. To minimize crosstalk 21 Place the 82562ET/EM part more than 1.5 inches from any board edge. This minimizes the potential of EMI radiation problems. 22 Verify the EEPROM size. 82562EM : 256 word TheIntel® 82562EM requires a larger EEPROM to store the alert envelope and other configuration information. 23 Place at least one bulk capacitor (≥ 4.
Intel® 820E Chipset R Table 49. CK-SKS Clocking # Layout Recommendations 1 CLK_33 goes to ICH2, FWH FLASH BIOS, and SIO. Clock chip to series resistor = 0.5 inch, and from series resistor to receiver = 15 inches max. Routed on one layer. 2 PCI_33 goes to PCI device or PCI slot. There are 5 clocks. Clock chip to series resistor = 0.5 inch, and from series resistor to receiver = 13 inches max. Routed on one layer. 3 CLK_66 goes to ICH2 and MCH. Clock chip to series resistor = 0.
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Intel® 820E Chipset R 3. Advanced System Bus Design Section 2.10 describes the recommendations for designing Intel 820E chipset-based platforms. This section discusses in more detail the methodology used to develop the advanced system bus guidelines. These layout considerations apply to Intel 820E chipset/FC-PGA designs. The design guidelines for the Pentium® III processor for the Intel PGA370 socket are found in the Intel® 820 Platform Design Guide Addendum, Revision 0.95. Section 3.
Intel® 820E Chipset R Term Flight time Definition Flight time is a timing equation term that includes the signal propagation delay, any effects of the system on the TCO of the driver, plus any adjustments to the signal at the receiver needed to guarantee the setup time of the receiver.
Intel® 820E Chipset R Term 3.2. Definition Simultaneous switching output (SSO) effects Difference in electrical timing parameters and degradation in signal quality caused by multiple signal outputs simultaneously switching voltage levels (e.g., high to low), in the direction opposite to a single signal (e.g., low to high) or in the same direction (e.g., high to low). These are respectively called odd-mode switching and even-mode switching.
Intel® 820E Chipset R 3.2.1. Initial Timing Analysis Perform an initial timing analysis of the system using the following two equations, which are the basis for timing analysis. To complete the initial timing analysis, values for clock skew and clock jitter are needed, along with the component specifications. These equations contain a multi-bit adjustment factor, MADJ, to account for multi-bit switching effects (e.g., SSO push-out or pull-in) that often are hard to simulate.
Intel® 820E Chipset R A designer using components other than those listed previously must evaluate additional combinations of driver and receiver. Table 51. AGTL+ Parameters for Example Calculations 1,2 Pentium® III Processor Core at 133 MHz Bus Intel® 82820 MCH Notes Clock-to-output maximum (TCO_MAX) 2.7 3.6 4 Clock-to-output minimum (TCO_MIN) -0.1 0.5 4 Setup time (TSU_MIN) 1.2 2.27 3,4 Hold time (THOLD) 0.8 0.28 4 IC Parameters NOTES: 1. All times in nanoseconds. 2.
Intel® 820E Chipset R The following two tables were derived assuming the following: • CLKSKEW = 0.2 ns Note: This assumes that clock driver pin-to-pin skew is reduced to 50 ps by tying two host clock outputs together (“ganging”) at the clock driver output pins, and the PCB clock routing skew is 150 ps. The system timing budget must assume 0.175 ns of clock driver skew if outputs are not tied together and a clock driver that meets the CK98 clock driver specification is being used. • CLKJITTER = 0.
Intel® 820E Chipset R 1 Table 53. Example TFLT_MIN Calculations (Frequency Independent) Driver Receiver THOLD ClkSKEW TCO_MIN Recommended TFLT_MIN Processor2 Processor2 0.8 0.2 -0.1 1.2 0.28 0.2 -0.1 .58 0.8 0.2 0.5 .5 2 Processor 82820 MCH ® Intel 82820 MCH 2 Processor NOTES: 1. All times in nanoseconds. 2. Processor values specified in this table are examples only. Refer to the appropriate processor datasheet for the specification values. 3.2.2.
Intel® 820E Chipset R 3.2.3.3. Monte Carlo Analysis Perform a Monte Carlo Analysis to refine the passing solution space region. A Monte Carlo Analysis involves randomly varying parameters independently of one another, over their tolerance ranges. This analysis is designed to ensure that no region of failing flight time and signal quality exists between the extreme corner cases run in pre-layout simulations.
Intel® 820E Chipset R The transmission line package models must be inserted between the output of the buffer and the net it is driving. Likewise, the package model must also be placed between a net and the input of a receiver model. This is performed, generally, by editing the simulator’s net description or topology file. Intel has found wide variation in noise margins when varying the stub impedance and the PCB’s Z0 and S0.
Intel® 820E Chipset R AGTL+. Intragroup AGTL+ crosstalk involves interference between AGTL+ signals within the same group. (See Section 3.4 for a description of the different AGTL+ group types.) Intergroup AGTL+ crosstalk involves the interference of AGTL+ signals in a particular group with AGTL+ signals in a different group. An example of AGTL+-to-non-AGTL+ crosstalk is when CMOS and AGTL+ signals interfere with each other. Table 54.
Intel® 820E Chipset R Figure 74. PICD[1,0] Uniprocessor Topology 1.5 Intel® PGA370 150Ω ICH2 Z0 = 60 Ω ± 15% picd_uniprocessor_topo Figure 75. PICD[1,0] Dual-Processor Topology 1.5 V 300–330 Ω 1.5 V Intel® PGA370 ICH2 Intel PGA370 300 –330 Ω Z0 = 60 Ω ± 15% picd_dual-processor_topo 3.2.5. Post-Layout Simulation After layout, extract the interconnect information for the board from the CAD layout tools. Run simulations to verify that the layout satisfies the timing and noise requirements.
Intel® 820E Chipset R 3.2.5.2. Crosstalk Analysis AGTL+ crosstalk simulations can consider as non-coupled the processor core package, the Intel 82820 MCH package, and the Intel PGA370 socket. Simulate the traces as lossless for worst-case crosstalk and lossy where more accuracy is needed. Evaluate both odd-mode and even-mode crosstalk conditions. AGTL+ crosstalk simulation involves the following cases: • Intragroup AGTL+ crosstalk • Intergroup AGTL+ crosstalk • Non-AGTL+ to AGTL+ crosstalk 3.2.5.3.
Intel® 820E Chipset R Figure 76. Test Load vs. Actual System Load VTT I/O Buffer RTEST Driver pad Vcc D CLK SET Q Test load Driver pin CLR Q TREF TCO I/O Buffer Driver pad Vcc CLK D VTT Actual system load RTT SET Q Receiver pin CLR Q TFLIGHTSYSTEM test_actual_load The previous figure shows the different configurations for TCO testing and flight time simulation. The flip-flop represents the logic input and driver stage of a typical AGTL+ I/O buffer.
Intel® 820E Chipset R 3.3. Theory 3.3.1. AGTL+ AGTL+ is the electrical bus technology used for the processor bus. This is an incident wave switching, open-drain bus with external pull-up resistors that provide both the high logic level and termination at each load. The processor AGTL+ drivers contain a full-cycle active pull-up device to improve system timings.
Intel® 820E Chipset R 3.3.3. Crosstalk Theory AGTL+ signals swing across a smaller voltage range and have a correspondingly smaller noise margin than technologies traditionally used in personal computer designs, so designers using AGTL+ must be more aware of crosstalk than they may have been in previous designs. Crosstalk is caused through capacitive and inductive coupling between networks. Crosstalk appears as both backward and forward crosstalk.
Intel® 820E Chipset R Additional aggressors are possible in the z-direction, if adjacent signal layers are not routed in mutually perpendicular directions. Because crosstalk coupling coefficients decrease rapidly with increasing separation, it is rarely necessary to consider aggressors at least five line widths away from the victim. The maximum crosstalk occurs when all aggressors are switching in the same direction at the same time.
Intel® 820E Chipset R 3.4. More Details and Insight 3.4.1. Textbook Timing Equations The “textbook” equations used to calculate the propagation rate of a PCB are the basis for spreadsheet calculations of timing margin based on the component parameters. These equations are as follows: Equation 9. Intrinsic Impedance Z0 = (L0 / C0)½ (Ω) Equation 10. Stripline Intrinsic Propagation Speed S0_STRIPLINE = 1.017 × εr½ (ns/ft) Equation 11. Microstrip Intrinsic Propagation Speed S0_MICROSTRIP = 1.
Intel® 820E Chipset R 3.4.2. Effective Impedance and Tolerance/Variation The impedance of the PCB must be controlled when the PCB is fabricated. The best impedance control specification method for each situation must be determined. The use of stripline transmission lines (where the trace is between two reference planes) is likely to yield better results than microstrip (where the trace is on an external layer, using an adjacent plane for reference, with solder mask and air on the other side of the trace).
Intel® 820E Chipset R 3.4.3.2. Reference Planes and PCB Stack-Up It is strongly recommended that baseboard stack-up be arranged such that AGTL+ signals are referenced to a ground (VSS) plane, and that the AGTL+ signals do not traverse multiple signal layers. Deviating from either guideline can create discontinuities in the signal’s return path, that can lead to large SSO effects that degrade the timing and noise margin.
Intel® 820E Chipset R Figure 81. Layer Switch with Multiple Reference Planes (Same Type) Signal Layer A Ground Plane Layer Layer Ground Plane Signal Layer B lay_sw_mult_refplane When routing and stack-up constraints require that an AGTL+ signal reference VCC or multiple planes, special care must be taken to minimize the SSO effect on timing and noise margin.
Intel® 820E Chipset R Figure 83. One Layer with Multiple Reference Planes Signal Layer A Ground Power 1lay_Mult_refplane 3.4.3.3. High-Frequency Decoupling This section contains several high-frequency decoupling recommendations that will improve the return path for an AGTL+ signal. These design recommendations will very likely reduce the amount of SSO effects.
Intel® 820E Chipset R 3.4.4. Clock Routing Analog simulations are required to ensure that the clock net signal quality and skew are acceptable. The system clock skew must be minimized. (The calculations and simulations for the example topology in this document have a total clock skew of 200 ps and 150 ps of clock jitter). For a given design, the clock distribution system, including the clock components, must be evaluated to ensure that these same values are valid assumptions.
Intel® 820E Chipset R 3.5.1. VREF Guard Band To account for noise sources that may affect the way an AGTL+ signal becomes valid at a receiver, VREF is shifted by ∆VREF for measuring the minimum and maximum flight times. The VREF guard band region is bounded by VREF – ∆VREF and VREF + ∆VREF. ∆VREF has a value of 100 mV, which accounts for the following noise sources: • Motherboard coupling • VTT noise • VREF noise 3.5.2.
Intel® 820E Chipset R 3.5.4. Flight Time Definition and Measurement Timing measurements consist of minimum and maximum flight times, to take into account the fact that devices can turn on or off anywhere in a VREF guard band region. This region is bounded by VREF – ∆VREF and VREF + ∆VREF. The minimum flight time for a rising edge is measured from the time the driver crosses VREF when terminated to a test load, to the time when the signal first crosses VREF – ∆VREF at the receiver (see Figure 85).
Intel® 820E Chipset R 4. Clocking 4.1. Clock Generation Two clock generator components are required in an Intel 820E chipset-based system. The Direct RDRAM clock generator (DRCG) generates clock for the Direct RDRAM interface, while the CK133 component generates clocks for the rest of the system. Clock synthesizers that meet the Intel CK98 Clock Specification are suitable for an Intel 820E chipset-based system. The CK133 generates the clocks listed in the following table. Table 55.
Intel® 820E Chipset R The MCH uses the same clock for hub interface and AGP. It is important that the hub interface/AGP clocks are routed so as to ensure that the skew requirements are satisfied as follows: • Between the MCH hub interface/AGP clock and the AGP connector (or device) • Between the MCH hub interface/AGP clock and the ICH2 hub interface clock The DRCG reference clock operates at one-half the processor clock frequency.
Intel® 820E Chipset R Table 56. Intel® 820E Chipset Platform Clock Skews Clock Symbols (see Figure 86) Relationship Skew Pin-to-Pin (ps) A leads C PGA370 HCLK to PGA370 Board (ps) Notes Total (ps) Min. Max. Min. Max. Min. Max.
Intel® 820E Chipset R The following figure shows the Intel 820E chipset clock length routing guidelines. 1,2 Figure 87. Intel® 820E Chipset Clock Routing Guidelines CPUCLK to SC242 CPUCLK to MCH Y Y 5.3" ±0" Note: Tie CPUCLK for the MCH to CPUCLK to the SC242, to eliminate pin-to-pin skew. 3V66 clock for AGP slot Z PCI clock for PCI slots Z 3V66 clock for MCH and ICH Z 4" Z 4" Z 4" PCI clock for ICH PCI clock for on-board devices (excluding ICH) 1.5" ±TBD3 ±0" ±0" ±TBD3 Note: 1.
Intel® 820E Chipset R Table 57.
Intel® 820E Chipset R 4.2. Component Placement and Interconnection Layout Requirements The layout requirements for each interconnection are explained in detail in the following sections: • Crystal to CK133 • CK133 to DRCG • MCH to DRCG • DRCG to RDRAM channel 4.2.1. 14.318 MHz Crystal to CK133 The distance between the crystal and the CK133 should be minimized. The maximum trace length is 500 mils. 4.2.2. CK133 to DRCG • Processor _div2 • VddIR – Used as a reference for 2.5 V signaling Figure 88.
Intel® 820E Chipset R 4.2.3. MCH to DRCG • PclkM • PclkN • VddIPD Figure 89. MCH-to-DRCG Routing Diagram 6 mils 6 mils Ground 6 mils VddiPD 6 mils 6 mils Ground 6 mils Hclkout 6 mils 6 mils 6 mils Rclkout 6 mils Ground 6 mils 1.4 mils 4.5 mils Ground/Power Plane 1.4 mils mch_drcg_route Hclkout, Rclkout, and VddIPD should be routed as shown in Figure 89. Note that the VddIPD pin can be connected directly to 1.8 V near the DRCG, if the 1.8 V plane extends near the DRCG.
Intel® 820E Chipset R 4.2.4. DRCG-to-RDRAM Channel The Direct RDRAM clock signals (CTM/CTM# and CFM/CFM#) are high-speed, impedance-matched transmission lines. Direct RDRAM clocks begin at the end of the Direct RDRAM channel and propagate to the controller as CTM/CTM# (see Figure 90), where they loop back as CFM/CFM#. The following table lists the placement guidelines. Table 58.
Intel® 820E Chipset R For line section D (DRCG to last RIMM), the CTM/CTM# must be length-matched within ±2 mils. (Exact matching is recommended.) For section C, ±2 mil trace length matching is required for the CFM/CFM# signals. Note: The total trace length matching for the entire CTM/CTM# signal trace (sections A+B+D) and for the CFM/CFM# signal trace (sections A+B) is ±2 mils. (Exact length matching is recommended.) Figure 91.
Intel® 820E Chipset R 4.3. DRCG Impedance Matching Circuit The external DRCG impedance matching circuit is shown in the following figure. The values for the elements are listed in Table 59. Figure 94. DRCG Impedance Matching Network 3.3 V To 3.3-V DRCG supply connection CD2 C C D V DD IR V Z CH R D R D R S C DRCG C CD2 S P F R C D MID P Z CH CD drcg_imped_match 1,2 Nominal Value Notes CD 0.
Intel® 820E Chipset R 4.3.1. DRCG Layout Example Figure 95. DRCG Layout Example Cmid - 100pF EMI Cap - 4pF Do Not Stuff CTM/CTM# route on bottom layer Rs - 39 Ω (Keep trace from DRCG to Rs VERY short) Rp - 51 Ω (Keep trace from Rs to Rp short) Decoupling Cap - 0.1uF (Place VERY Near DRCG 3.3V Pin!) Decoupling Cap - 0.1uF (Place VERY Near DRCG 3.3V Pin!) 3.3V-DRCG Flood Flood 3.3V-DRCG on the top layer around DRCG. Flood MUST include: 4 DRCG Power Pins 4 0.
Intel® 820E Chipset R 4.7. Unused Outputs All unused clock outputs must be tied to ground through a series resistor that has approximately the impedance of the output buffer (shown in the following table). These resistors are designed to terminate unused outputs to eliminate EMI. Table 60. Unused Output Termination Buffer Name 4.8. VCC Range (V) Impedance (Ω Ω) If Unused Output Ω) Termination to Vss (Ω CPU, CPU_Div2, IOAPIC 2.375 – 2.625 13.5 – 45 30 48 MHz, REF 3.135 – 3.
Intel® 820E Chipset R 4.9. DRCG Frequency Selection and the DRCG+ 4.9.1. DRCG Frequency Selection Table and Jitter Specification To provide additional flexibility in board design, Intel has enabled a variation of the DRCG, called the DRCG+. The device has the same specifications, pinout, and form-factor mentioned in the document for the existing DRCG device. Two modifications were made to the DRCG+. 1. The DRCG+ Mult[0:1] select table was changed to modify two of the multiplier ratios.
Intel® 820E Chipset R 4.9.2. DRCG+ Frequency Selection Schematic The DRCG+ frequency can be selected using two GPIOs connected to the MULT[0:1] pins, as shown in the following figure. This allows selection of all frequencies supported by the Intel 820E chipset. REFCLK PWRD# STOPB# MULTO MULT1 S0 S1 GND PCLKM SYNCLKN NC CLK CLKB# 20 18 17 21 4 8 5 GNDO1 GNDO2 GNDP GNDC GNDI GPO1 GPO2 2 12 11 15 14 24 23 13 6 7 19 VDDIR VDDIPD VDDO1 VDDO2 VDDP VDDC U? DRCG 1 10 16 22 3 9 Figure 96.
Intel® 820E Chipset R 5. System Manufacturing 5.1. Stack-Up Requirement The Intel 820E chipset platform requires a board stack-up with a 4.5 mil prepreg. This change in dimension (previously, typically 7 mils) is required because of the signaling environment used for the Direct RDRAM, AGP 2.0, and hub interface. The RDRAM channel is designed for 28 Ω, and mismatched impedance will cause signal reflections that will reduce the voltage and timing margins.
Intel® 820E Chipset R 5.1.2. Design Process To meet the tight tolerances required, a good design process is as follows: • Specify the material to be used. • Calculate the board geometries for the desired impedance or use the example stack-up provided. • Build test boards and coupons. • Measure the board impedance using a TDR and follow Intel’s Impedance Test Methodology Document (located on the developer.intel.com web site). • Measure geometries with cross section.
Intel® 820E Chipset R 5.1.4. Recommended Stack-Up Though numerous stack-up variations are possible, the following starting point is recommended: W = 18 mils, H = 4.5 mils, T = 2.0, 1-ply 2116 prepreg For other possibilities see the following table and the following figures: Table 61. 28 Ω Stack-Up Examples 5.1.5. Sample Zo H W T SM (max.) Resin % 1 27.1 4.3 18.0 2.1 0.6 53.0 2 28.1 3.8 18.5 1.6 1.2 72.0 3 28.6 4.8 19.0 2.5 0.7 61.
Intel® 820E Chipset R Figure 98. Microstrip (a) and Stripline (b) Cross Section for 28 Ω Trace a) Microstrip cross section for 28-Ω trace 10 mils 18 mils 6 mils S G 2.1 mils G 4.5 mils b) Stripline cross section for 28-Ω trace 1.2 mils 6 mils 7 mils 13.5 mils 5 mils G S G 1.2 mils 5 mils 1.2 mils x-section_28trace Note: 5.1.6. Do not forget ground floods and stitching.
Intel® 820E Chipset R 5.1.7. Testing Board Impedance The Intel Printed Circuit Board (PCB) Test Methodology document (order# 298179-001) should be used to ensure boards are within the 28Ω +/- 10% requirement. This document can be found at http://developer.intel.com. 5.1.8. Board Impedance/Stack-up Summary 1. 7628 cloth (1-ply, 0.007 inch when cured with 40% resin) is the most popular and highest-volume in PCB production today. This stack-up will make routing impossible.
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Intel® 820E Chipset R 6. System Design Considerations 6.1. Power Delivery 6.1.1. Terminology and Definitions Term Definition Suspend to RAM (STR) In the STR state, the system state is stored in main memory and all unnecessary system logic is turned off. Only main memory and logic required to wake the system remain powered. This state is used in the Customer Reference Board to satisfy the S3 ACPI power management state.
Intel® 820E Chipset R 6.1.2. Power Delivery of Intel® 820E Chipset Customer Reference Board Figure 101 shows the power delivery architecture for the Intel 820E Chipset Reference Board. This power delivery architecture supports the Instantly Available PC Design Guidelines via the Suspend-toRAM (STR) state. During STR, only the necessary devices are powered. These devices include main memory, the ICH2 resume well, PCI wake devices (via 3.3 VAUX), and USB.
Intel® 820E Chipset R This design guide provides only examples. Many power distribution methods achieve similar results. When deviating from these examples in any way, it is critical to consider the effects of the change. In addition to the power planes provided by the ATX power supply, an instantly available Intel 820E chipset-based system (using Suspend to RAM) requires that seven power planes be generated on the board. The requirements for each power plane are documented in this section.
Intel® 820E Chipset R 2.5 VBSY The 2.5 VSBY power plane is used to power the RDRAM core and the VCMOS rail on the RDRAMs. The RDRAM core requires an approximately 4.5-A maximum average DC current at 2.5 V. In the Intel 820E chipset reference board, the 2.5 VSBY plane is derived from the 5 V dual power plane using a switching regulator. During the maximum load-step of 2 A, the maximum voltage fluctuation must be less than 50 mV. The maximum tolerance for 2.5 V is 125 mV.
Intel® 820E Chipset R Figure 102. 1.8 V and 2.5 V Power Sequencing (Schottky Diode) 1.8 V 2.5 V diode_1.8V&2.5V VDDQ The VDDQ plane is used to power the MCH AGP interface and the graphics component AGP interface. Refer to the AGP Interface Specification, Revision 2.0 (http://www.agpforum.org). For long-term component reliability, the following power sequence is strongly recommended while the AGP interface of the MCH is running at 3.3 V. If the AGP interface is running at 1.
Intel® 820E Chipset R 1.8 VSB The 1.8 VSB plane powers the logic to the resume well of the ICH2. This should not be used for VCMOS. The VCMOS described in the 2.5 VSBY section should be powered down in S5. However, the 1.8 VSB requires power in S5. Refer to the 2.5 VSBY section for information regarding powering the VCMOS (1.8 V) rail. 2.5 V The 2.5 V plane supplies power to the CK133 and the DRCG system clock generator components. 6.1.3. ICH2 1.8 V / 3.
Intel® 820E Chipset R Figure 103. Example 1.8V/3.3V Power Sequencing Circuit +1.8V +3.3V 220 220 Q2 NPN Q1 PNP 470 When analyzing systems that may be “marginally compliant” with the 2 V Rule, pay close attention to the behavior of the ICH2’s RSMRST# and PWROK (also LAN_PWROK in ICH2-m) signals, since these signals control the internal isolation logic between the various power planes, as follows: • RSMRST# controls the isolation between the RTC well and the resume wells.
Intel® 820E Chipset R Figure 104. Example 3.3V/5V REF Sequencing Circuitry VCC Supply (3.3 V) 5 V Supply 1K 1 µF To System VREF To System 6.1.5. Excessive Power Consumption by 64/72-Mbit RDRAM Some 64/72-Mbit RDRAM devices interpret non-broadcast, device-directed commands as broadcast commands. These commands are the SET_FAST_CLOCK, SET_RESET, and CLEAR_RESET commands. RDRAM devices consume more current during these initialization steps than during normal operation.
Intel® 820E Chipset R Figure 105. Use a GPO to Reduce DRCG Frequency S0 DRCG GPO S0 gpo_drcg-freq 6.1.5.2. Option 2: Increase the Current Capability of the 2.5 V Voltage Regulator The second implementation option requires that the 2.5 V power supply be modified to maintain the maximum amount of current required by a fully populated RDRAM channel (~7.5 A).
Intel® 820E Chipset R 6.2. ICH2 Power Plane Split The following example shows the power plane splits for the ICH2. Figure 106.
Intel® 820E Chipset R 6.3. Thermal Design Power The thermal design power is the estimated maximum possible expected power generated in a component by a realistic application. It is based on extrapolations of both hardware and software technology over the life of the product. It does not represent the expected power generated by a power virus.
Intel® 820E Chipset R More information regarding this component is available from the vendors listed in the following table. Table 64. Glue Chip Vendors Vendor Intel Fujitsu Microelectronics Contact Customer Response Center Contact Information 3545 North 1st Street, M/S 104 San Jose, CA 95134-1804 Phone: 1-800-866-8600 Fax: 1-408-922-9179 E-mail: fmicrc@fmi.fujitsu.
Intel® 820E Chipset R Appendix A: Reference Design Schematics (Uniprocessor) This chapter provides the schematic diagrams for the Reference Board Uniprocessor design.
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A B C D 7 6 5 6 2 8 Rev is ion His tory 7 39 42 40, 41 RA MBUS Dec oupling Dec oupling 38 PCI/A GP Pullups /Pulldow ns 37 A GTL Termination V RM 36 32 33 Game Port Pow er Connec tor 31 Key board/Mous e/Floppy Ports 34, 35 30 Serial Ports V oltage Regulators 28 29 27 IDE Connec tors Parallel Port 25,26 PCI Connec tors USB Connec tors 23 24 A GP Connec tor 19,20,21,22 Sy s tem 15,16,17,18, LA N 12 Super I/O LA N 11 RIMM Soc kets 13,14 10 FW H A udio 8, 9 ICH
8 7 LPC Bus 6 Mouse Keyboard SIO Floppy VTERM A FWH AC’97 Link PCI ADDR/DATA DRCG 5 Serial 2 Serial 1 Parallel Game Conn 82562EH/ET CNR LAN PCI CONN 1 Modem AC’97 Audio USB Port 2 ICH2 ADDR USB ADDR USB Port 1 CTRL PCI CNTRL RIMM 0 IDE Secondary MCH CTRL UltraDMA/100 AGP Bus Rambus Clock 5 PCI CONN 2 B AGP Processor 6 DATA IDE Primary VRM Block Diagram 7 DATA C D 8 4 4 PCI CONN 4 PCI CONN 3 RIMM 1 U25 U26 U27 U28 3 2 2 1 1 REV: 0.
A B C 8 HD#[63:0] 7 HD#0 HD#1 HD#2 HD#3 HD#4 HD#5 HD#6 HD#7 HD#8 HD#9 HD#10 HD#11 HD#12 HD#13 HD#14 HD#15 HD#16 HD#17 HD#18 HD#19 HD#20 HD#21 HD#22 HD#23 HD#24 HD#25 HD#26 HD#27 HD#28 HD#29 HD#30 HD#31 HD#32 HD#33 HD#34 HD#35 HD#36 HD#37 HD#38 HD#39 HD#40 HD#41 HD#42 HD#43 HD#44 HD#45 HD#46 HD#47 HD#48 HD#49 HD#50 HD#51 HD#52 HD#53 HD#54 HD#55 HD#56 HD#57 HD#58 HD#59 HD#60 HD#61 HD#62 HD#63 W1 T4 N1 M6 U1 S3 T6 J1 S1 P6 Q3 M4 Q1 L1 N3 U3 H4 R4 P4 H6 L3 G1 F8 G3 K6 E3 E1 F12 A5 A3 J3 C5 F6 C1 C7 B2 C9
A B C 4 4 5 8 1 NC1 5 NC5 9 NC9 13 NC13 16 NC16 3 DXP 4 DXN THERMDP_R R122 0K R121 0K CPURST#_R2 R521 110 1% 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 C436 7 4.7UF 2 1 SMBCLK_CORE SMBDATA_CORE THRM# VCC3_3 R519 182 1% SMBCLK 14 SMBDATA 12 ALERT# 11 ADD0 10 ADD1 6 STBY# 15 U9 ADM1021 THERMDP J28 0.
A B C VCC3_3 R206 D 0.1UF JP15 0.1UF 10K R197 O UT IN IN O UT O UT 0 1 1 1 1 0.1UF O UT IN O UT IN O UT JP 17 IN O UT IN JP 14 IN OUT 10K 0.1UF JP19 is for debug only. SEL133/100# PCISTOP# CPUSTOP# CK133_PWRDWN# SPREAD# SEL1 SEL0 10PF C185 8 1 2 14.
A B C D 3,37 8 HD#[63:0] MCH HD#0 HD#1 HD#2 HD#3 HD#4 HD#5 HD#6 HD#7 HD#8 HD#9 HD#10 HD#11 HD#12 HD#13 HD#14 HD#15 HD#16 HD#17 HD#18 HD#19 HD#20 HD#21 HD#22 HD#23 HD#24 HD#25 HD#26 HD#27 HD#28 HD#29 HD#30 HD#31 HD#32 HD#33 HD#34 HD#35 HD#36 HD#37 HD#38 HD#39 HD#40 HD#41 HD#42 HD#43 HD#44 HD#45 HD#46 HD#47 HD#48 HD#49 HD#50 HD#51 HD#52 HD#53 HD#54 HD#55 HD#56 HD#57 HD#58 HD#59 HD#60 HD#61 HD#62 HD#63 7 R2 R1 R4 P5 T1 R5 V1 Y2 W1 U1 T2 Y3 W2 U3 Y1 U2 W4 W3 V4 U4 T3 Y4 Y5 T4 V5 T5 Y6 W5 U6 V6 W6 T6 W
A B C 8 24 24 7 24,38 24,38 24,38 24,38 24,38 24,38 24 24,38 24,38 5 24,38 24,38 24,38 24,38 24,38 24,38 24,38 24,38 24,38 GC/BE#[3:0] ST0 ST1 ST2 ST[2:0] ADSTB0 ADSTB#0 ADSTB1 ADSTB#1 SBSTB SBSTB# 6 J19 H20 R18 R19 Y20 Y19 W15 Y15 Y17 AD_STB0 AD_STB#0 AD_STB1 AD_STB#1 SB_STB SB_STB# ST0 ST1 ST2 V16 RBF# V15 WBF# RBF# WBF# G_FRAME# G_DEVSEL# G_IRDY# G_TRDY# G_STOP# G_PAR G_REQ# G_GNT# PIPE# G_C/BE#0 G_C/BE#1 G_C/BE#2 G_C/BE#3 G_AD0 G_AD1 G_AD2 G_AD3 G_AD4 G_AD5 G_AD6 G_AD7 G_AD8 G_AD
A B C VCC1_8 8 R10 1% 330 7,9,34,36 4,9,33,36 9,34,36 4,8,36 9,35 6,8,10,11,12,24,25,26,27 9,36 4,6,37 D CR3 2 1 Led Blink with GPIO 25,26 2 4 6 8 10 12 14 16 18 20 22 24 26 28 C_BE#[3:0] J17 7 TP3 TP4 26 5 25,26,38 25,26,38 25,26,38 25,26,38 25,26,38 25,26 6,8,10,11,12,24,25,26,27 25,26,38 25,26,38 25,26,38 VCC3_3 24,25,26 1 3 5 7 9 11 13 15 17 19 21 23 25 27 Test header. For debug only.
A B C + 3 R161 1K VBAT_RTC 2 1 A C- VBAT_CR BAT17 D ICH2 CR5 C148 8 9,23 2 1 2 1 No Stuff A JP5 C129 JP18 2.7K 2 1 32.768KHZ C130 7 AC_SDATAOUT No Stuff AC_SDOUT_STRAP 2.7K VCC3_3 8.2K R157 VCC3_3 JP11 4 8.2K 4,11,15,38 4,11,15,38 38 8,34,36 8,35 7,8,34,36 8,9,36 23 30 8,9,36 TP2 TP7 8.
0K R306 0K R305 8 7 10K 0K R299 VCC3_3 6 VCC3_3 5 4.7K 5 1 R296 FWH_IC 2 8.2K 3 4 5 6 R298 FGPI4 7 8.2K 8 FWHPCLK 9 10 VPP_R 11 PCIRST# 12 13 14 R300 FGPI3 15 FGPI2 16 8.2K FGPI1 17 FGPI0 18 19 20 WPROT TBLK_LCK 8.2K R303 R308 6,8,11,12,24,25,26,27 JP21 VCC3_3 Top Block Lock R304 A B S100DETECT P100DETECT For drive side detection, stuff R304,R307. No stuff R305,R306. For host side detection, stuff R304,R305,R306,R307. 27 27 0.1UF C C305 Do not tie Vpp to 12V.
A B C D 8 4,9,11,15,38 4,9,11,15,38 6,11 RAMREF LCOL[4:0] LROW[2:0] LDQB[8:0] VCC3_3 SWP 0.1UF SMBCLK_CORE SMBDATA_CORE 7 7 7 7 7 7 7 7 7 7 7 LDQA[8:0] As shown, RIMMs are 184-pin connectors. RIMM Sockets R226 4.7K R228 4.
A B C D IRRX IRTX KBDAT KBCLK MDAT MCLK 8,12,26,38 8 SERIRQ 7 1 3 5 7 9 11 13 15 17 19 21 23 25 27 J20 2 4 6 8 10 12 14 16 18 20 22 24 26 28 7 LPC header. For debug only. 470PF 470PF 5 31 31 31 31 31 31 31 31 31 31 31 31 31 31 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 8,38 8,38 9 8,12,26,38 5,12 9,10,12 9,10,12 9,10,12 4.7K 9,10,12 9,10,12 9,12 6,8,10,11,12,24,25,26,27 VCC3_3 C317 4.
A B C 1 + 8 10UF 2 C83 0.1UF C62 23 1 VIN 3 L17 2 AC97_SPKR 1 GND 4 +5V VR2 MC78M05CDT 7 10K R67 VCC5_AUDIO 1 + 14 14 14 14 14 14 14 14 AGND 10UF 2 C57 D C85 0.1UF LNLVL_OUT_R LNLVL_OUT_L CD_R CD_L CD_REF 6 1UF-TANT 2 C70 1 + No stuff C358. C358 0.1UF AC97_SPKR_R AGND 13,14 LINE_IN_R LINE_IN_L MIC_IN 0.
A B C 13 J4 1 2 3 4 8 2 MIC_IN_C CD_R_J CD_L_J CD_REF_J 4.7K R18 4.7K R27 4.7K R52 AGND + 1UF-TANT C25 1 2 LINE_IN_L + 1UF-TANT 1 C23 AGND 0.
J18 2 4 6 8 R60 7 EE_CS_ICH2_OB EE_CS_ICH2 10K 5% R59 8 10K 5% 1 3 5 7 10K 5% VCC3_3 10K 5% 21 9,15 R58 A B C D 16 16 16 16 16 16 16 16 VCC3_3 6 VCC3_3SBY A10 B9 A7 B8 A8 B11 A11 B12 A18 B19 B15 A19 A3 A6 A9 A14 A17 A20 A30 B4 B24 A23 A24 EE_SHCLK_ICH2 B22 EE_DOUT_ICH2 A21 B21 EE_DIN_ICH2 A22 EE_CS_ICH2 SMBCLK_CORE B25 SMBDATA_COREA25 LAN_CLK_CNR LAN_RST_CNR LAN_TXD2_CNR LAN_TXD1_CNR LAN_TXD0_CNR LAN_RXD2_CNR LAN_RXD1_CNR LAN_RXD0_CNR VCC5SBY 9,21 9,21 9,21 9,15 4,9,11,38 4,9
A B C D 7 6 5 8 7 8 8 8 8 8 8 8 8 LAN_CLK_ICH2 LAN_RXD2_ICH2 LAN_RST_ICH2 LAN_RXD1_ICH2 LAN_TXD2_ICH2 LAN_RXD0_ICH2 LAN_TXD0_ICH2 LAN_TXD1_ICH2 6 9 9 9 AC_SDATAOUT_ICH2 AC_SDATAIN0_ICH2 AC_SYNC_ICH2 22 OHMS ARE PROVIDED TO MINIMIZE STUBS ON AC97 LINK 5 ICH2 AC97 AND CNR LINK STUFFING OPTIONS 8 0K 5% RP49 0K 5% RP7 8 7 6 5 8 7 6 5 22 5% 22 5% RP51 RP50 8 7 6 5 8 7 6 5 1 2 3 4 1 2 3 4 22 5% 22 5% RP53 RP52 8 7 6 5 8 7 6 5 Stuff for LAN Down 1 2 3 4 1 2 3 4 Stuff
A 8 7 18 C286 6 16,18 16,18 16,18 16,18 PHAD_ISOL_PINS NOTE: FOR HOME LAN CONFIGURATION STUFF ALL COMPONENTS ON THIS PAGE 6 0.1UF 20% LAN_CLK LAN_RXD0 R346 10K R364 1K R341 1K LAN_TXD0 10K R365 R90 LAN_RESET 1% 1K 20 1% 2 1 17 18 19 20 21 3 4 22 23 26 25 42 31 39 34 32 30 43 44 45 46 10 20 1% 1% 100 1K 1% 5 C12 VCC3_3SBY 0.
A B C D 8 7 LAN (82562ET/EM) 7 17 17,21 17,21 16,17 16 16,17 16,17 16 16,17 16 16 5 ISOL_TEX ISOL_TCK ISOL_TI ADV10 TOUT 29 30 28 41 26 PHAD_ISOL_PINS 6 VCC3_3SBY 5 JRESET JRXD_2 JCLK JRXD_0 JRXD_1 JTXD_0 JTXD_1 JTXD_2 46 X1 47 X2 42 37 39 34 35 43 44 45 U25 LAN_CLK_X1 LAN_CLK_X2 LAN_RESET LAN_RXD2 LAN_CLK LAN_RXD0 LAN_RXD1 LAN_TXD0 LAN_TXD1 LAN_TXD2 NOTE: FOR HOME LAN CONFIGURATION EMPTY ALL COMPONENTS ON THIS PAGE 6 VCCP-40 40 VCCP-36 36 25 VCC-25 1 VCC-1 VCC3_3SBY 8 VSS-8 13 V
A B C D 7 8 7 18,20,21 18,20,21 18,20 18,20 LAN_RDP LAN_RDM LAN_TDM LAN_TDP LAN (RJ11 For 82562EH) 8 R335 0K 6 RDC/GND 10 C333 1500PF 20% 2KV TXP 12 CMT 11 TXM 9 NC9 8 NC8 7 RXP/RING 6 RXM/TIP 5 RXC A03449-001 U28 16 TDP 14 TDC 15 TDM 13 NC13 4 NC4 1 RDP/CHIP+ 2 RDM//CHIP3 L25 4.
A B C D 7 8 7 18,19,21 18,19,21 18,19 18,19 LAN_RDP LAN_RDM LAN_TDM LAN_TDP LAN (RJ45 For 82562ET/EM) 8 6 0.1UF C318 RDC/GND RXC 10 TXP 12 CMT 11 TXM 9 NC9 8 NC8 7 RXP/RING 6 RXM/TIP 5 H1138_ARAGONITE U27 16 TDP C329 14 TDC 0.
A 8 17 C291 7 GILAD_RDM VCC3_3SBY 2 GILAD_RDP 25MHZ B 17 Y5 XTAL 6 121 1% R381 R382 10K 1% R95 806 1% 1% 51.1 1% 51.1 6 0.
A B C D 8 LAN 8 7 VCC3_3SBY 7 0.1UF 20% 25V C380 0.1UF 20% 25V C376 4.7UF 20% 16V C366 0.1UF 20% 25V C381 0.1UF 20% 25V C377 6 0.1UF 20% 25V C386 0.1UF 20% 25V C382 0.1UF 20% 25V C378 4.7UF 20% 16V C369 STUFF FOR 82562EH STUFF FOR GILAD ONLY AND 82562ET/EM 6 5 5 0.1UF 20% 25V C385 4.7UF 20% 16V C370 0.1UF 20% 25V C384 0.1UF 20% 25V C383 0.1UF 20% 25V C379 4.7UF 20% 16V C375 4 STUFF FOR 82562ET/EM ONLY 4 3 2 0.1UF 20% 25V C388 0.
27 8 VCC3_3SBY R289 9 U19 SN74LVC07A SBY_LED_CR 1 U19 SPKR 6 JP1 2.2K R103 1 1 Q15 VCC3_3 2 3 2 3 2.2K R101 9 5 13 470PF 1 2 3 SN74LVC07A 3 U14 GND VCC 4 6 5 4 VCC3_3SBY C1 B2 E2 VCC5 IRTX IRRX VCC3_3 4 U26 FFB3904 E1 B1 C2 VCC3_3SBY AC97_SPKR 2.2K R98 GPIO23_FPLED 2.2K R100 12 470PF VCC3_3 470 12 12 R356 KEYLOCK# HDLED_R C355 No stuff.
A B C D 8 8,25,26,38 AGP Connector 7 7 7 7 GAD[31:0] GC/BE#[3:0] PIRQ#B 5 ST[2:0] SBA[7:0] VCC3_3SBY 7 7 28 VCC5 AGP_OC# VCC3_3 5 6 5 B1 B2 B3 USBAGP+ B4 28 B5 B6 B7 AGPCLK_CONN GREQ# B8 7,38 B9 B10 ST0 B11 ST2 B12 RBF# 7,38 B13 B14 B15 SBA0 B16 B17 SBA2 SBSTB B18 7,38 B19 B20 SBA4 B21 SBA6 B22 B23 B24 B25 B26 GAD31 B27 GAD29 B28 B29 GAD27 B30 GAD25 B31 ADSTB1 B32 7,38 B33 GAD23 B34 B35 GAD21 B36 GAD19 B37 B38 GAD17 B39 GC/BE#2 B40 GIRDY# B41 7,38 B42 B43 B44 B45 B46 GDEVSEL# 7,38 B47
A B C D VCC3_3 AD[31:0] 8,26 8 C_BE#[3:0] 8,26 PRSNT#12 PIRQ#B PIRQ#D PRSNT#11 PTCK 25 AD1 AD5 AD3 AD8 AD7 AD12 AD10 PU1_ACK64# SERR# PLOCK# PERR# C_BE#1 AD14 8,25,26,38 8,25,26,38 8,25,26,38 8,25,26,38 IRDY# DEVSEL# AD17 C_BE#2 AD21 AD19 C_BE#3 AD23 AD27 AD25 AD31 AD29 PREQ#0 PCLK1 8,25,26,38 8,38 5 25 25 8,24,25,26,38 8,25,26,38 25,26 VCC12- VCC5 7 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B
A B C D AD[31:0] 8,25 8 C_BE#[3:0] 8,25 5 SERR# PLOCK# PERR# DEVSEL# PU3_ACK64# AD1 AD5 AD3 AD8 AD7 AD12 AD10 C_BE#1 AD14 8,25,26,38 8,25,26,38 8,25,26,38 8,25,26,38 IRDY# AD17 C_BE#2 AD21 AD19 8,25,26,38 26 PREQ#2 PCLK3 PRSNT#32 PIRQ#A PIRQ#C PRSNT#31 PTCK C_BE#3 AD23 AD27 AD25 AD31 AD29 8,38 26 8,24,25,26,38 8,25,26,38 26 25,26 VCC3_3 7 7 VCC12- VCC5 PCI Connectors 2 and 3 8 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B
A B C 9 8 PDREQ 9 27 VCC3_3 PCIRST_BUF# 9 9 8,38 PDA[2:0] PIORDY 4.7K D 9 R336 PDD[15:0] 7 PDA2 9 23 33 R333 PDCS#1 IDEACTP# PDIOW# PDIOR# PDDACK# IRQ14 PDA1 PDA0 9 9 PDD7 PDD6 PDD5 PDD4 PDD3 PDD2 PDD1 PDD0 J22 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 PDCS#3 IDE_JP PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15 9 P100DETECT 10 6 5 For drive side detection, stuff C329,C318. For host side detection, no stuff C329,C318.
8 OC#1 OC#0 0.1UF C120 0.1UF C109 24 R97 10K R87 VCC3_3 AGP_OC# 7 2 8 5 1 Do Not Stuff 0.1UF IN OC#1 OC#2 GND 7 6 3 4 USBP1P USBP1N C245 47PF 47PF USBPWR2_F 15 R244 15 47PF C241 5 USBP1P_R USBP1N_R 15-1% R242 15-1% R240 2 68UF-TANT C98 L11 4 L10 1 1 0K 0.1UF C43 USB-_CNR USB+_CNR 0K R501 470PF C38 2 3 470PF C37 USBG1 47PF 47PF 2 1 2 3 4 5 6 7 8 J3 2 1 REV: 0.5 PROJECT: Camino2 SHEET: 28 OF 40 C39-C42 for test and debug only.
A B C 8 12 12 12 12 12 12 12 12 12 12 AFD# STB# ERR# 7 SLIN# PAR_INIT# PDR[7:0] ACK# BUSY PE SLCT 33 6 1 2 3 4 33 RP18 33 RP19 RP20 1 2 3 4 PDR3 PDR2 8 7 6 5 1 2 3 4 PDR7 PDR6 PDR5 PDR4 PDR1 PDR0 3 8 7 6 5 8 7 6 5 PDR1_R PDR0_R AFD#_R STB#_R PDR3_R PDR2_R SLIN#_R PAR_INIT#_R PDR7_R PDR6_R PDR5_R PDR4_R VCC5_DB25_CR C81 CR1 1 MMBD914LT1 5 CP2 4 180PF 3 6 180PF 5 180PF CP2 D CP2 2 VCC5 CP2 7 180PF Parallel Port 5 4 1 8 180PF 5 180PF CP3 6 3 6 180PF 2
A B C D 9 8 ICH_RI# 2 3 2 3 Q1 1 VCC3_3SBY 1 7 RI_Q RI_CR C92 3 2 CR2 BAT54C 1 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 6 6 DCD#1 RXD1 DSR#1 DTR#1 TXD1 CTS#1 RTS#1 RI#1 DCD#0 RXD0 DSR#0 DTR#0 TXD0 CTS#0 RTS#0 RI#0 VCC5 VCC5 20 19 18 17 16 15 14 13 12 11 20 19 18 17 16 15 14 13 12 11 5 GD75232 VCC VCC12 RY0 RA0 RY1 RA1 RY2 RA2 DA0 DY0 DA1 DY1 RA3 RY3 DA2 DY2 RY4 RA4 GND VCC-12 U6 GD75232 VCC VCC12 RA0 RY0 RY1 RA1 RA2 RY2 DA0 DY0 DA1 DY1 RY3 RA3 DY2 DA2 RY4 RA4 GND VCC
A B C 8 12 12 12 1 1 MCLK 1 KBCLK MDAT 1 KBDAT 7 L13 L14 L12 L16 2 2 2 2 2 L15 6 C46 GND_KBMS_C C47 VCC5_KBMS_J 12 C32 2 C33 MCLK_FB MDAT_FB KBCLK_FB KBDAT_FB 1 C45 VCC5_KBMS_F 100PF 1.0A 100PF F1 100PF 1 100PF 12 VCC5 0.
8 7 6 5 4 470PF C56 + C55 47PF 50V 2 0.01UF 25V 10% 47 5% 1 C54 47PF 3 50V 2 C52 47PF 50V C51 47PF 50V VCC5 MIDI_IN_R JOY1Y_R JOY2Y_R MIDI_OUT_R JOY1X_R JOY2X_R 2 J5 DB15_AUD_STK 31 1 9 2 10 3 11 4 12 5 13 6 14 7 15 8 32 1 2 TITLE: INTEL(R) 820E CHIPSET 2 DIMM FCPGA REFERENCE BOARD GAME PORT DRAWN BY: PCG PLATFORM DESIGN R PCG AE 1900 PRAIRIE CITY ROAD LAST REVISED: FOLSOM, CALIFORNIA 95630 1 REV: 0.
A B C 3 8 VID[3:0] 7 C90 R80 JP6 L19 0.1UF Place caps next to output FETs. C82,C87,C107,C111,C467-C471 must support >11A of RMS current. 0.33UH VRM_VCC5 DO3316P-331HC VCC5 2 JP8 JP10 JP7 6 C87 2 1 + 1200UF C111 2 1 + 1200UF C107 2 1 + 1200UF C82 1 + 1200UF D 10K 1 + 10UF C140 2 OUTEN C467 1 + 1200UF 2 C468 1 + 1200UF 2 VRM requirements are based on VRM8.4 spec .
A B C 8,9,36 7,8,9,36 1 VCC3_3 2 1 2 VCC 2 2 1 3 VIN VR4 LT1585A GND 1 VOUT 2 ADJ 1 VOUT 2 VR8 LT1587ADJ 7 VCC 1.8 VOLTAGE REGULATOR 3 VIN VD_G2 VCC1_8_ADJ 2 1 VTT 1.5 VOLTAGE REGULATOR VD_G1 GND SN74LVC07A 1 U14 VCC3_3SBY R330 2 1 1K 1K R340 B 6 1 Q13 VCC1_8 VD_G3 VCC5DUAL_R Place C311 at regulator.
A B 8,9 8 VCC3_3SBY SLP_S5# VCC2_5SBY SN74LVC07A 7 7 GND C294 C293 6 VCC5DUAL VCC3_3SBY C296 C292 1 D1 2 S1 3 S2 4 G1 D3 8 S4 7 S3 6 D2 5 Q20 SI6467DQ D3 8 S4 7 S3 6 D2 5 5 1 2 1 2 VCC5SBY VCC3_3SBY 4 A VCC5SBY 1 + 100UF 2 8 7 6 5 0.1UF Q19 SI9426DY D1 S1 D2 S2 D3 S3 D4 G1 2 1 G1 S3 S2 S1 SI9426DY Q11 D4 D3 D2 D1 5 6 7 8 1 2 3 4 4 3 2 1 A + C- 10UH CDRH127-6R1 L23 3 VIN 3 ADJ 1VCC1_8SBY_ADJ VOUT 2 VR9 LT1587ADJ C426 + 100UF 0.01 C304 Do not stuff C304.
A B C D 4 8,9,34 VCC3_3SBY R536 10K VCOREDET# 8 PS_ON# PS_ON 74LVC14A7 13 U15 14 4,8,9,33 VCOREDET VCC5 7 JP12 SW2 Reset Button 12 VCC3_3SBY SLP_S3# SN74LVC06A has 5V output tolerance. GND SN74LVC06A7 U20 14VCC 5 6 VCC3_3SBY VCC5SBY 14 U3 11 1 2 3 4 5 6 7 8 9 10 VCC3_3 ATX_PWOK VCC12 VCC5SBY 6 22 R343 C328 10UF C335 0.01UF 220 ohm pullup to VCC3_3 is located on VRM sheet.
A B C D 7 8 VTT1_5 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 62 RP28 62 RP27 62 RP26 62 RP25 62 RP24 62 RP23 62 RP22 62 RP21 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 HA#17 HA#24 HA#30 HA#18 HA#11 HA#14 HA#21 HA#15 HA#13 HA#9 HA#3 HA#12 HA#5 HA#19 HA#26 HA#27 HA#20 HA#22 HA#7 HA#4 HA#6 HA#16 HA#28 HA#10 HA#25 HA#31 HA#23 HA#29 7 HREQ#4 HREQ#2 DEFER# BPRI# HA#[31:3] AGTL Termination 8 4,6 4,6 3,6 3,6 3,6 6 VT
A B C D 7 8 9 9 9 STOP# PLOCK# PERR# SERR# SMLINK_DATA SMLINK_CLK SMB_ALERT SMBDATA_CORE 7 4.7K R13 4.7K R235 4.7K R237 4.7K R12 4.7K 2.7K RP11 2.7K RP10 2.7K RP6 8.2K R89 1 2 3 4 2.7K R213 2.7K R115 2.7K R112 1 2 3 4 1 2 3 4 1 2 3 4 8.2K R81 8.2K R114 8.2K R214 8.2K RP16 2.7K R109 2.7K R216 2.7K R111 R323 8.2K R236 8.
A B C D 8 11 11 11 11 TERM_COL[4:0] TERM_ROW[2:0] TERM_DQB[8:0] TERM_DQA[8:0] 7 TERM_COL3 TERM_COL4 TERM_ROW2 TERM_COL0 TERM_COL1 TERM_COL2 TERM_DQB7 TERM_DQB8 TERM_ROW0 TERM_ROW1 TERM_DQB3 TERM_DQB4 TERM_DQB5 TERM_DQB6 TERM_DQA8 TERM_DQB0 TERM_DQB1 TERM_DQB2 TERM_DQA4 TERM_DQA5 TERM_DQA6 TERM_DQA7 TERM_DQA0 TERM_DQA1 TERM_DQA2 TERM_DQA3 28-1% 28-1% 28-1% 28-1% 28-1% 28-1% 28-1% 28-1% 28-1% 28-1% 28-1% 28-1% 28-1% 28-1% 28-1% 28-1% 28-1% 28-1% 28-1% 28-1% 28-1% 28-1% 28-1% 28-1% 2
0.1UF 10 9 10 U3 8 8 SN74LVC08A 7 14 VCC3_3SBY 74LVC14A7 11 U15 14 VCC3_3SBY 7 7 GND U18 74LS132 14VCC 12 11 13 7 GND U18 74LS132 14VCC 1 3 2 VCC5SBY For chipset decoupling, use 0.1UF and 0.01UF decoupling capacitor at each corner of the device. If there is room, also add 0.01UF capacitor in the middle of each quad. Place additional caps if routable. 0.1UF 0.01UF Backside No Stuff 0.1UF 0.01UF 0.01UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF MCH Decoupling VCC1_8 0.
A B C C216 C125 C143 C153 C154 C151 C181 8 0.1UF VCC3_3SBY 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 7 + 22UF C342 2 0.1UF 1 0.1UF 0.1UF VCC5 VCC12 0.1UF Bulk Power Decoupling 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF VCC2_5 Decoupling VCC2_5 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF VCC3_3 Decoupling VCC3_3 0.
A B C D 8 8 7 7 6 6 5 5 4 Revision History 4 3 3 1 2 1 TITLE: INTEL(R) 820E CHIPSET 2 DIMM FCPGA REFERENCE BOARD REVISION HISTORY DRAWN BY: PCG PLATFORM DESIGN R PCG AE 1900 PRAIRIE CITY ROAD LAST REVISED: FOLSOM, CALIFORNIA 95630 3-20-2000_10:14 2 REV: 0.
A B C D 7 8 7 Hub Interface Connector For debug only.
