Datasheet

Intel
®
Itanium
®
Processor 9300 Series and 9500 Series Datasheet 149
System Management Bus Interface
6.2.2 Scratch EEPROM
Intel
®
Itanium
®
Processor 9300 Series and Intel
®
Itanium
®
Processor 9500 Series
support a Scratch EEPROM section, which may be used for other data at the system
vendor’s discretion. The data in this EEPROM, once programmed, can be write-
protected by asserting the active-high SM_WP signal. This signal has a weak pull-down
(10 kΩ) to allow the EEPROM to be programmed in systems with no implementation of
this signal. The Scratch EEPROM resides in the upper half of the memory component
(addresses 80 - FFh). The lower half comprises the Processor Information ROM
(addresses 00 - 7Fh), which is permanently write-protected.
Features
114 72h Processor Core Feature
Flags
RESERVED
(Intel® Itanium®
Processor 9500 Series)
8 digit Hex
number
From CPUID
Reserved for future use (Intel®
Itanium® Processor 9500 Series)
Flag = 0x4387FBFF
72h = 0xFF
73h = 0xFB
74h = 0x87
75h = 0x43
(Intel® Itanium®
Processor 9300 Series)
72h = 0x00
73h = 0x00
74h = 0x00
75h = 0x00
(Intel® Itanium®
Processor 9500 Series)
115 73h
116 74h
117 75h
118 76h RESERVED Hex Reserved for future use 76h = 0x00
77h = 0x00
119 77h
120 78h Package Feature Flags Hex Bit[7:4] reserved
Bit[3] = THERMALERT_N
threshold values present
Bit[2] = SCRATCH EEPROM
present
Bit[1] = Core VID present
Bit[0] reserved
where a 1 indicates valid data
Flag = 0x000E
78h = 0x0E
79h = 0x00
121 79h
122 7Ah RESERVED Hex Reserved for future use 7Ah = 0x00
123 7Bh Number of Devices in
TAP Chain
Hex Bits [7:4] Number Devices in
processor TAP chain
Bits [3:0] Reserved
5 devices for Intel®
Itanium® Processor
9300 Series = 0x50
9 devices for Intel®
Itanium® Processor
9500 Series = 0x90
124 7Ch Checksum Hex Add up by byte and take 2's
complement
Other
125 7Dh RESERVED Hex Reserved for future use 7Dh = 0x00
7Eh = 0x00
7Fh = 0x00
126 7Eh
127 7Fh
Table 6-1. Processor Information ROM Data (Sheet 6 of 6)
Sec # Offset Field Name Data Type Description Example