Datasheet

System Management Bus Interface
152 Intel
®
Itanium
®
Processor 9300 Series and 9500 Series Datasheet
6.4 PIROM Field Definitions
PIROM data is divided into sections containing similar data. Each section contains
specific fields defined in the following sections.
6.4.1 General
To maintain backward compatibility, the General section defines the starting address for
each subsequent section of the PIROM. Software should check for the offset before
reading data from a particular section of the ROM.
The General section begins with offset 00h which contains Data Format Revision
information, followed by the EEPROM size, both formatted in Hex bytes. The data
format revision is used whenever fields within the PIROM are updated with new values.
Normally the revision would begin at a value of 1. If a field, or bit assignment within a
field, is changed such that software needs to discern between the old and new
definition, then the data format revision field should be incremented.
6.4.2 Processor Data
This section contains following pieces of data:
• Sample or Production field to identify a pre-production sample or a production unit.
• Required voltage regulator field
• VCCA and VCCIO voltage specs.
The sample or production field is a two-bit, LSB-aligned value. 0x00 indicates unlocked
PIROM section. This is the case in most samples. 0x01 indicates a locked PIROM
section. Some samples and all production parts will be locked.
The required voltage regulator field for the Intel
®
Itanium
®
Processor 9300 Series is
0x00. The required voltage regulator field for the Intel® Itanium® Processor 9500
Series is 0x01.
6.4.3 Processor Core Data
This section contains silicon-related data relevant to the processor cores.
6.4.3.1 CPUID
Offset 22h-25h contains a copy of the results in EAX[31:0] from Function 1 of the
CPUID instruction.
6.4.3.2 Boost Core Frequency
Offset 26h-27h provides the boost core frequency for the processor. The frequency
should equate to the markings on the processor even if the parts are not limited or
locked to the intended speed. Format of this field is in MHz, rounded to a whole
number, and encoded as four 4 bit-bcd digits. Offset 26h contains the core count for the
Intel
®
Itanium
®
Processor 9500 Series, while offset 27h is RESERVED for the Intel
®
Itanium
®
Processor 9500 Series.
Example: For the Intel® Itanium® processor 9300 series, the 1733 GHz processor will
have a value of 1733. For the Intel
®
Itanium
®
Processor 9500 Series eight core SKU,
0x26 will have a value of 8.