Datasheet

Signal Definitions
162 Intel
®
Itanium
®
Processor 9300 Series and 9500 Series Datasheet
FBD1NBI[C/D][P/N][12:0] I These differential pair data signals generated from the branch one, channel C and D
of FB-DIMMs are input to the processor.
Example: FBD1NBICP[0] represents FB-DIMM branch 1, northbound data input lane
0 signal of channel C and positive bit of the differential pair.
FBD1NBI[C/D][P/N][13] I These signals are spare lanes, and are intended for Reliability, Availability, and
Serviceability (RAS) coverage on the Intel
®
Itanium
®
9500 Processor Series. These
signals are not used by Intel
®
Itanium
®
9300 Processor Series.
FBD0SBO[A/B][P/N][9:0] O These differential pair output data signals generated from the processor to the
branch zero, channel A and B of FB-DIMMs.
Example: FBD0SBOAP[0] represents FB-DIMM branch 1, southbound data output
lane 0 signal of channel A and positive bit of the differential pair.
FBD0SBO[A/B][P/N][10] O These signals are spare lanes, and are intended for Reliability, Availability, and
Serviceability (RAS) coverage on the Intel
®
Itanium
®
9500 Processor Series. These
signals are not used by Intel
®
Itanium
®
9300 Processor Series.
FBD1SBO[C/D][P/N][9:0] O These differential pair output data signals generated from the processor to the
branch one, channel C and D of FB-DIMMs.
Example: FBD1SBOCP[0] represents FB-DIMM branch 1, southbound data output
lane 0 signal of channel C and positive bit of the differential pair.
FBD1SBO[C/D][P/N][10] O These signals are spare lanes, and are intended for Reliability, Availability, and
Serviceability (RAS) coverage on the Intel
®
Itanium
®
9500 Processor Series. These
signals are not used by Intel
®
Itanium
®
9300 Processor Series.
FLASHROM_CFG[2:0] I These are input signals to the processor that would initialize and map the Flash
ROM upon reset. After reset is deasserted this input would be ignored by the
processor logic. These pins are sampled during all resets except warm-logic reset.
FLASHROM_CLK O The Flash ROM clock.
FLASHROM_CS[3:0]_N O Flash ROM chip selects. Up to four separate flash ROM parts may be used.
FLASHROM_DATI I Serial Data Input (from ROM(s) to processor).
FLASHROM_DATO O Serial Data Output (from processor to ROM(s))
FLASHROM_WP_N O Flash ROM write-protect.
Table 7-1. Signal Definitions for the Intel
®
Itanium
®
Processor 9300 Series and Intel
®
Itanium
®
9500 Series (Sheet 4 of 8)
Name Type Description
FB-
DIMM
1 NB I C/D P/N [12:0]
Interface
Name
Branch
Number
North
Bound
Input Channel Differential
Pair
Polarity
Positive/
Negative
Lane
Number
FB-
DIMM
0SBOA/BP/N[9:0]
Interface
Name
Branch
Number
South
Bound
Output Channel Differential
Pair
Polarity
Positive/
Negative
Lane
Number
FB-
DIMM
1NBOC/DP/N[9:0]
Interface
Name
Branch
Number
North
Bound
Output Channel Differential
Pair
Polarity
Positive/
Negative
Lane
Number