Datasheet

Intel
®
Itanium
®
Processor 9300 Series and 9500 Series Datasheet 69
Electrical Specifications
2.13 Timing Relationship Between RESET_N and SKTID
In the processor, the SKTID pins are time-shared:
SKTID[0] is interpreted as a NodeID bit during cold reset and pwrgood reset. It is
interpreted as the error reset modifier during warm-logic reset if SKTID[0] is asserted.
SKTID[2] is interpreted as a NodeID bit during cold reset and pwrgood reset, and it is
interpreted as an error input being signaled by the system at all other times (except
during non-cold resets when it is ignored). Figure 2-20 and Table 2-40 show the timing
relationship between RESET_N and SKTID pins for different reset cases.
The LRGSCLSYS pin is sampled only during the PWRGOOD and cold reset period.
The BOOTMODE[2:0] and FLASHROM_CFG[1:0] pins are sampled during the assertion
of all resets except warm-logic resets.
Figure 2-19. Supported Power-down Voltage Sequence Timing Requirements
RESET_N
PWGOOD
VR_OUTPUT_EN
(133 MHz)
VIDs
VCCCORE
VCCUNCORE
VCCA
VCCCACHE
REFCLK
VCCIO
t
RESET_N
A s fast as p ossible
All supplies to power down as fast as
Possible after PW RGOOD deassertion
> 1us
> 0us
VCCA MUST UNPOWER ALONG WITH VCCIO
t
RESET_N
= 10ms for Intel Itanium 9300 Series Processor
= 1 5 m s for P ou lson-M C P rocessor
> =0us
All signal inputs on VCCIO plane can power down with VCCIO
change to safe VID