Datasheet

Electrical Specifications
70 Intel
®
Itanium
®
Processor 9300 Series and 9500 Series Datasheet
Figure 2-20. RESET_N and SKITID Timing for Warm and Cold Resets
Table 2-40. RESET_N and SKTID Timing (Sheet 1 of 2)
Parameter Description MIN MAX UNIT
T1
PWRGOOD deasserted delay to RESET_N
asserted
0 200 ns
T2
PWRGOOD asserted delay to RESET_N
deasserted (Intel® Itanium® Processor 9300
Series)
10 ms
T2
PWRGOOD asserted delay to RESET_N
deasserted (Intel® Itanium® Processor 9500
Series)
15 ms
T3
RESET_N setup and hold relative to SYSCLK
asserted
500 ps
T4
RESET_N deasserted pulse width
8
SYSCLK
cycles
T5
RESET_N asserted pulse width (Intel® Itanium®
Processor 9300 Series)
10 ms
T5
RESET_N asserted pulse width (Intel® Itanium®
Processor 9500 Series)
15 ms
T6
SKTID[2:0] (as rst modifier, error) hold after
PWRGOOD deasserted
0ns
T7
SKTID[2:0] (as socket id), LRGSCLSYS,
BOOTMODE[2:0], FLASHROM_CFG[1:0] setup to
PWRGOOD deasserted
0ns
T8
SKTID[2:0] (as socket id), LRGSCLSYS hold
after RESET_N deasserted
0ns
T9
SKTID[1:0] (as rst modifier) setup to RESET_N
asserted
200 ns
T10
SKTID[1:0] (as rst modifier) hold after RESET_N
asserted
200 ns
BOOTMODE[2:0]
FLASHROM
_CFG
[1:0]
PWRGOOD
RESET_N
SKTID[1:0]
T2
T
5
T4
SKTID[2]
LRGSCLSYS
socket id
Error Reset
(Warm-Logic) if
SKTID [
0
]==1
socket id
error_in
strap value
T9
T7
T8
T 11
T 13
T 13
T10
(PWR CYCLE OR PWRGOOD)
COLD RESET
WARM-
STATE OR WARM -
LOGIC RESETS
T12
T 14
strap values strap values
T1
T6
T3 T3
SYSCLK