Datasheet

Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family 113
Datasheet Volume Two: Functional Description, February 2014
Processor Uncore Configuration Registers
13.2.2.4 SSRSTATUS
Provides the status of a spare-copy memory Init operation.
3:2 RW_LB 0x0
CHANNEL SELECT FOR THE SPARE COPY (chn_sel):
Since there is only one spare-copy logic for all channels, this field selects the
channel or channel-pair for the spare-copy operation.
For independent channel operation:
00 = channel 0 is selected for the spare-copy operation
01 = channel 1 is selected for the spare-copy operation
10 = channel 2 is selected for the spare-copy operation
11 = channel 3 is selected for the spare-copy operation
For lock-step channel operation:
0x = channel 0 and channel 1 are selected for the spare-copy operation
1x = channel 2 and channel 3 are selected for the spare-copy operation
1:1 RV - Reserved.
0:0 RW_LBV 0x0
SPARE_ENABLE (spare_enable):
Spare enable when set to 1. Hardware clear after the sparing completion. This
bit shall be mutex wit DDDCSPARECTL.SPARE_ENABLE.
Type: CFG PortID: N/A
Bus: 1 Device: 15 Function: 1
Bus: 1 Device: 29 Function: 1
Offset: 0x90
Bit Attr Default Description
Type: CFG PortID: N/A
Bus: 1 Device: 15 Function: 1
Bus: 1 Device: 29 Function: 1
Offset: 0x94
Bit Attr Default Description
31:3 RV - Reserved.
2:2 RW1C 0x0
PATCMPLT (patcmplt):
All memory has been scrubbed. Hardware sets this bit each time the patrol
engine steps through all memory locations. If software wants to monitor 0 --
-> 1 transition after the bit has been set, the software will need to clear the
bit by writing a one to clear this bit in order to distinguish the next patrol
scrub completion. Clearing the bit will not affect the patrol scrub operation.
1:1 RO_V 0x0
SPRCMPLT (sprcmplt):
Spare Operation Complete. Set by hardware once operation is complete. Bit
is cleared by hardware when a new operation is enabled.
Note: just before MC release the HA block prior to the completion of the
sparing operation, iMC logic will automatically update the corresponding
RIR_RNK_TGT target to reflect new DST_RANK.
0:0 RO_V 0x0
SPRINPROGRESS (sprinprogress):
Spare Operation in progress. This bit is set by hardware once operation has
started. It is cleared once operation is complete or fails.