Datasheet

Processor Uncore Configuration Registers
116 Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
13.2.2.8 SPAREINTERVAL
Defines the interval between normal and sparing operations. Interval is defined in dclk.
13.2.2.9 RASENABLES
RAS Enables Register
13.2.2.10 SMISPARECTL
Scalable Memory Interconnect Spare control register.
Type: CFG PortID: N/A
Bus: 1 Device: 15 Function: 1
Bus: 1 Device: 29 Function: 1
Offset: 0xa8
Bit Attr Default Description
31:29 RV - Reserved.
28:16 RW 0x320
NUMSPARE (numspare):
Sparing operation duration. System requests will be blocked during this interval
and only sparing copy operations will be serviced.
15:0 RW 0xc80
NORMAL OPERATION DURATION (normopdur):
Normal operation duration. System requests will be serviced during this
interval.
Type: CFG PortID: N/A
Bus: 1 Device: 15 Function: 1
Bus: 1 Device: 29 Function: 1
Offset: 0xac
Bit Attr Default Description
31:1 RV - Reserved.
0:0 RW_LB 0x0
MIRROREN (mirroren):
Mirror mode enable. The channel mapping must be set up before this bit will
have an effect on iMC operation. This changes the error policy.
Type: CFG PortID: N/A
Bus: 1 Device: 15 Function: 1
Bus: 1 Device: 29 Function: 1
Offset: 0xb4
Bit Attr Default Description
31:18 RV - Reserved.
17:17 RW 0x0
INTRPT_SEL_PIN (intrpt_sel_pin):
Enable pin signaling. When set the interrupt is signaled via the ERROR_N[0] pin
to get the attention of a BMC.
16:16 RW 0x0
INTRPT_SEL_CMCI (intrpt_sel_cmci):
(CMCI used as a proxy for NMI signaling). Set to enable CMCI (NMI) signaling.
Clear to disable CMCI (NMI) signaling. If both CMCI (NMI) and SMI enable bits
are set then only SMI is sent