Datasheet
Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family 117
Datasheet Volume Two: Functional Description, February 2014
Processor Uncore Configuration Registers
13.2.2.11 LEAKY_BUCKET_CFG
The leaky bucket is implemented as a 53-bit DCLK counter. The upper 42-bit of the 53-
bit counter is captured in LEAKY_BUCKET_CNTR_LO and LEAKY_BUCKET_CNTR_HI
registers. The carry “strobe” from the not-shown least significant 11-bit counter will
trigger this 42-bit counter-pair to count.
LEAKY_BUCKET_CFG contains two hot encoding thresholds LEAKY_BKT_CFG_HI and
LEAKY_BKT_CFG_LO. The 42-bit counter-pair is compared with the two thresholds pair
specified by LEAKY_BKT_CFG_HI and LEAKY_BKT_CFG_LO. When both counter bits
specified by the LEAKY_BKT_CFG_HI and LEAKY_BKT_CFG_LO are set, the 53-bit leaky
bucket counter will be reset and the logic will generate a “Primary Leak Strobe” which is
used by a 2-bit LEAKY_BKT_2ND_CNTR_REG.LEAKY_BKT_2ND_CNTR_LIMIT specifies
the value to generate LEAK pulse which is used to decrement the correctable error
counter by 1 as shown below table:
Note: A value of all zeroes in LEAKY_BUCKET_CFG register is equivalent to no leaky
bucketing.
15:15 RW 0x0
INTRPT_SEL_SMI (intrpt_sel_smi):
SMI enable. Set to enable SMI signaling. Clear to disable SMI signaling.
14:0 RV - Reserved.
Type: CFG PortID: N/A
Bus: 1 Device: 15 Function: 1
Bus: 1 Device: 29 Function: 1
Offset: 0xb4
Bit Attr Default Description
LEAKY_BKT_2ND_CNTR_LIMIT LEAK pulse to decrement CE counter by 1
00b (Default)
4x Primary leak strobe (four times the value programmed by the
LEAKY_BKT_CFG_HI and LEAKY_BKT_CFG_LO)
01b
1x Primary leak strobe (same as the value programmed by the
LEAKY_BKT_CFG_HI and LEAKY_BKT_CFG_LO)
10b
2x Primary leak strobe (two times the value programmed by the
LEAKY_BKT_CFG_HI and LEAKY_BKT_CFG_LO)
11b
3x Primary leak strobe (two times the value programmed by the
LEAKY_BKT_CFG_HI and LEAKY_BKT_CFG_LO)
Type: CFG PortID: N/A
Bus: 1 Device: 15 Function: 1
Bus: 1 Device: 29 Function: 1
Offset: 0xb8
Bit Attr Default Description
31:12 RV - Reserved.