Datasheet

Processor Uncore Configuration Registers
120 Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
13.2.3.1 PXPCAP
13.2.3.2 DIMMMTR_[0:2]
DIMM Memory Technology.
DIMMMTR_2 0x88 32
PXPENHCAP 0x100 32
Type: CFG PortID: N/A
Bus: 1 Device: 15 Function: 2,3,4,5
Bus: 1 Device: 29 Function: 2,3,4,5
Offset: 0x40
Bit Attr Default Description
31:30 RV - Reserved.
29:25 RO 0x0
Interrupt Message Number (interrupt_message_number):
N/A for this device
24:24 RO 0x0
Slot Implemented (slot_implemented):
N/A for integrated endpoints
23:20 RO 0x9
Device/Port Type (device_port_type):
Device type is Root Complex Integrated Endpoint
19:16 RO 0x1
Capability Version (capability_version):
PCI Express Capability is Compliant with Version 1.0 of the PCI Express
Spec.
Note:
This capability structure is not compliant with Versions beyond 1.0, since
they require additional capability registers to be reserved. The only purpose
for this capability structure is to make enhanced configuration space
available. Minimizing the size of this structure is accomplished by reporting
version 1.0 compliancy and reporting that this is an integrated root port
device. As such, only three Dwords of configuration space are required for
this structure.
15:8 RO 0x0
Next Capability Pointer (next_ptr):
Pointer to the next capability. Set to 0 to indicate there are no more
capability structures.
7:0 RO 0x10
Capability ID (capability_id):
Provides the PCI Express capability ID assigned by PCI-SIG.
Register name Offset Size
Type: CFG PortID: N/A
Bus: 1 Device: 15 Function: 2,3,4,5
Bus: 1 Device: 29 Function: 2,3,4,5
Offset: 0x80, 0x84, 0x88
Bit Attr Default Description
31:20 RV - Reserved.