Datasheet

Processor Uncore Configuration Registers
122 Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
13.2.3.3 PXPENHCAP
This field points to the next Capability in extended configuration space.
13.2.4 Device 16, 30 Functions 0, 1, 4, 5
The Device 16 and 30 Function 0, 1, 4 and 5 contains Thermal Control registers. The
registers in Device 16 Functions 0, 1, 4, 5 are identical to those in Device 30 Functions
0, 1, 4, 5, respectively. The Device 16 Function 0, 1, 4 and 5 registers address iMC 0
Channel 2, 3, 0 and 1, while the Device 30 Function 0, 1, 4 and 5 registers address iMC
1 Channel 2, 3, 0 and 1.
4:2 RW_LB 0x0
RA_WIDTH (ra_width):
000 - Reserved
001 - Reserved
010 - 14 bits
011 - 15 bits
100 - 16 bits
101 - 17 bits HDRL, if DISABLE_EXTENDED_ADDR_DIMM is 1, setting 101
is decoded as 100.. (Such configuration is not supported)
110 - 18 bits HDRL, if DISABLE_EXTENDED_ADDR_DIMM is 1, setting 110
is decoded as 100. (Such configuration is not supported)
111: reserved
1:0 RW_LB 0x0
CA_WIDTH (ca_width):
00 - 10 bits
01 - 11 bits
10 - 12 bits
11 - reserved
Type: CFG PortID: N/A
Bus: 1 Device: 15 Function: 2,3,4,5
Bus: 1 Device: 29 Function: 2,3,4,5
Offset: 0x80, 0x84, 0x88
Bit Attr Default Description
Type: CFG PortID: N/A
Bus: 1 Device: 15 Function: 2,3,4,5
Bus: 1 Device: 29 Function: 2,3,4,5
Offset: 0x100
Bit Attr Default Description
31:20 RO 0x0
Next Capability Offset (next_capability_offset):
Indicates there are no capability structures in the enhanced configuration
space.
19:16 RO 0x1
Capability Version (capability_version):
Capability Version.
15:0 RO 0xb
Capability ID (capability_id):
Capability ID.
Register Name Offset Size
VID 0x0 16
DID 0x2 16