Datasheet

Processor Uncore Configuration Registers
130 Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
13.2.4.8 CHN_TEMP_CFG
Type: CFG PortID: N/A
Bus: 1 Device: 16 Function: 0,1,4,5
Bus: 1 Device: 30 Function: 0,1,4,5
Offset: 0x100
Bit Attr Default Description
31:20 RO 0x0
Next Capability Offset (next_capability_offset):
Indicates there are no capability structures in the enhanced configuration
space.
19:16 RO 0x1
Capability Version (capability_version):
Capability Version.
15:0 RO 0xb
Capability ID (capability_id):
Capability ID.
Type: CFG PortID: N/A
Bus: 1 Device: 16 Function: 0,1,4,5
Bus: 1 Device: 30 Function: 0,1,4,5
Offset: 0x108
Bit Attr Default Description
31:31 RW 0x1
OLTT_EN (oltt_en):
Enable OLTT temperature tracking
30:30 RV - Reserved.
29:29 RW 0x0
CLTT_OR_PCODE_TEMP_MUX_SEL (cltt_or_pcode_temp_mux_sel):
The TEMP_STAT byte update mux select control to direct the source to
update DIMMTEMPSTAT_[0:3][7:0]:
0: Corresponding to the DIMM TEMP_STAT byte from
PCODE_TEMP_OUTPUT.
1: TSOD temperature reading from CLTT logic.
28:28 RW_O 0x1
CLTT_DEBUG_DISABLE_LOCK (cltt_debug_disable_lock):
lock bit of DIMMTEMPSTAT_[0:3][7:0]:Set this lock bit to disable
configuration write to DIMMTEMPSTAT_[0:3][7:0]. When this bit is clear,
system debug / test software can update the DIMMTEMPSTAT_[0:3][7:0] to
verify various temperature scenarios.
27:27 RW 0x1 Enables thermal bandwidth throttling limit (bw_limit_thrt_en):
26:24 RV - Reserved.
23:16 RW 0x0
THRT_EXT (thrt_ext):
Max number of throttled transactions to be issued during BWLIMITTF due to
externally asserted MEMHOT#.
15:11 RV 0x0
Reserved:
Reserved.
10:0 RW 0x3ff
BW_LIMIT_TF (bw_limit_tf):
BW Throttle Window Size in DCLK