Datasheet

Processor Uncore Configuration Registers
134 Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
13.2.4.14 DIMMTEMPSTAT_[0:2]
10:10 RW 0x0
Assert MEMHOT Event on TEMPLO (ev_mh_templo_en):
Assert MEMHOT# Event on TEMPLO
9:9 RW 0x0
Assert MEMHOT Event on TEMPOEMHI (ev_mh_tempoemhi_en):
Assert MEMHOT# Event on TEMPOEMHI
8:8 RW 0x0
Assert MEMHOT Event on TEMPOEMLO (ev_mh_tempoemlo_en):
Assert MEMHOT# Event on TEMPOEMLO
7:4 RV - Reserved.
3:0 RW 0x0
DIMM_TEMP_OFFSET (dimm_temp_offset):
Bit 3-0 - Temperature Offset Register
Type: CFG PortID: N/A
Bus: 1 Device: 16 Function: 0,1,4,5
Bus: 1 Device: 30 Function: 0,1,4,5
Offset: 0x150 , 0x154, 0x158
Bit Attr Default Description
31:29 RV - Reserved.
28:28 RW1C 0x0
Event Asserted on TEMPHI going HIGH (ev_asrt_temphi):
Event Asserted on TEMPHI going HIGH
It is assumed that each of the event assertion is going to trigger Configurable
interrupt (Either MEMHOT# only or both SMI and MEMHOT#) defined in bit 30
of CHN_TEMP_CFG
27:27 RW1C 0x0
Event Asserted on TEMPMID going High (ev_asrt_tempmid):
Event Asserted on TEMPMID going High
It is assumed that each of the event assertion is going to trigger configurable
interrupt (Either MEMHOT# only or both SMI and MEMHOT#) defined in bit 30
of CHN_TEMP_CFG
26:26 RW1C 0x0
Event Asserted on TEMPLO Going High (ev_asrt_templo):
Event Asserted on TEMPLO Going High
It is assumed that each of the event assertion is going to trigger Configurable
interrupt (Either MEMHOT# only or both SMI and MEMHOT#) defined in bit 30
of CHN_TEMP_CFG
25:25 RW1C 0x0
Event Asserted on TEMPOEMLO Going Low (ev_asrt_tempoemlo):
Event Asserted on TEMPOEMLO Going Low
It is assumed that each of the event assertion is going to trigger Configurable
interrupt (Either MEMHOT# only or both SMI and MEMHOT#) defined in bit 30
of CHN_TEMP_CFG
Type: CFG PortID: N/A
Bus: 1 Device: 16 Function: 0,1,4,5
Bus: 1 Device: 30 Function: 0,1,4,5
Offset: 0x140, 0x144, 0x148
Bit Attr Default Description