Datasheet

14 Intel® Xeon® Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
14.10 Device 5 Function 4 I/OxAPIC............................................................................489
14.10.1INDEX.................................................................................................490
14.10.2WINDOW.............................................................................................490
14.10.3EOI.....................................................................................................490
14.10.4Device 5 Function 4 Window 0................................................................490
14.11 Device 6 Function 0, 3 and Device 7 Function 0 ...................................................496
14.11.1VID.....................................................................................................496
14.11.2DID ....................................................................................................497
14.11.3PCICMD...............................................................................................497
14.11.4PCISTS................................................................................................498
14.11.5RID.....................................................................................................499
14.11.6CCR....................................................................................................499
14.11.7CLSR...................................................................................................499
14.11.8PLAT...................................................................................................500
14.11.9HDR....................................................................................................500
14.11.10BIST..................................................................................................500
14.11.11SVID .................................................................................................500
14.11.12SDID.................................................................................................501
14.11.13CAPPTR..............................................................................................501
14.11.14INTL..................................................................................................501
14.11.15INTPIN...............................................................................................501
14.11.16MINGNT.............................................................................................502
14.11.17MAXLAT.............................................................................................502
14.11.18PXPCAP..............................................................................................502
14.11.19RX_CTLE_PEAK_GEN2..........................................................................503
14.11.20RX_CTLE_PEAK_GEN3..........................................................................503
Figures
2-1 Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
High Level Block Diagram ...................................................................................23
3-1 SAD Address Map ..............................................................................................31
5-1 Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family Memory Interface......40
6-1 Integrated I/O Module High-level Block Diagram....................................................45
6-2 PCI Express Lane Partitioning..............................................................................48
7-1 Error Classification.............................................................................................52
10-1 Power and Thermal Management Architecture Overview..........................................66
12-1 Processor integrated I/O device map....................................................................72
12-2 Processor uncore devices map.............................................................................73
Tables
1-1 Processor Terminology .......................................................................................18
1-2 Processor Documents.........................................................................................21
1-3 Public Specifications...........................................................................................21
2-1 Technologies in the Processor Core ......................................................................24
12-1 Functions specifically handled by the processor......................................................75
12-2 RW_LB CSRs list allowed PECI write when not in BMC_INIT mode ............................78
12-3 Register attribute definitions ...............................................................................79
14-1 BDF:BAR# for various MMIO BARs in IIO ............................................................189
14-2 Function number of active root ports in port 2(Dev#2) based on port bifurcation......190
14-3 Function number of active root ports in port 3(Dev#3) based on port bifurcation......190