Datasheet

Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family 147
Datasheet Volume Two: Functional Description, February 2014
Processor Uncore Configuration Registers
13.2.4.31 TCMRS
13.2.4.32 MC_INIT_STAT_C
State register per channel. Sets control signals static values. Power-up default is state
0x0 set by global reset.
BIOS should leave this register default to zero since PCU microcode has Read/Write
ODT table logic to control ODT dynamically during IOSAV or NORMAL modes.
13.2.5 Device 16, 30 Functions 2, 3, 6, 7
The Device 16 and 30 Function 2, 3, 6 and 7 contain Test registers. The registers in
Device 30 Functions 2, 3, 6, 7 are identical to those in Device 16 Functions 2, 3, 6, 7
respectively. The Device 16 Function 2, 3, 6 and 7 registers address iMC 0 Channel 2,
3, 0 and 1, while the Device 30 Function 2, 3, 6 and 7 registers address iMC 1 Channel
2, 3, 0 and 1.
Type: CFG PortID: N/A
Bus: 1 Device: 16 Function: 0,1,4,5
Bus: 1 Device: 30 Function: 0,1,4,5
Offset: 0x244
Bit Attr Default Description
31:4 RV - Reserved.
3:0 RW 0x8
TMRD_DDR3 (tmrd_ddr3):
DDR3 tMRD timing parameter. MRS to MRS minimum delay in number of DCLK.
Type: CFG PortID: N/A
Bus: 1 Device: 16 Function: 0,1,4,5
Bus: 1 Device: 30 Function: 0,1,4,5
Offset: 0x280
Bit Attr Default Description
31:6 RV - Reserved.
5:0 RW_L 0x0
CKE ON OVERRIDE (cke_on):
When set, the bit overrides and asserts the corresponding CKE[5:0] output
signal during IOSAV mode. When cleared, the CKE pin is controlled by the IMC
IOSAV logic.
Register Name Offset Size Functions
VID 0x0 16 2,3,6,7
DID 0x2 16 2,3,6,7
PCICMD 0x4 16 2,3,6,7
PCISTS 0x6 16 2,3,6,7
RID 0x8 8 2,3,6,7
CCR 0x9 24 2,3,6,7
CLSR 0xc 8 2,3,6,7
PLAT 0xd 8 2,3,6,7
HDR 0xe 8 2,3,6,7
BIST 0xf 8 2,3,6,7