Datasheet

Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family 159
Datasheet Volume Two: Functional Description, February 2014
Processor Uncore Configuration Registers
13.5.2.1 PXPCAP
13.5.2.2 PXPENHCAP
This field points to the next Capability in extended configuration space.
MINGNT 0x3e 8
MAXLAT 0x3f 8
PXPCAP 0x40 32
PXPENHCAP 0x100 32
FWDC_LCPKAMP_CFG 0x390 32
Type: CFG PortID: N/A
Bus: 1 Device: 8 Function: 4
Bus: 1 Device: 9 Function: 4
Bus: 1 Device: 24 Function: 4
Offset: 0x40
Bit Attr Default Description
31:30 RV - reserved.
29:25 RO 0x0
interrupt_message_number:
N/A for this device
24:24 RO 0x0
slot_implemented:
N/A for integrated endpoints
23:20 RO 0x9
device_port_type:
Device type is Root Complex Integrated Endpoint
19:16 RO 0x1
capability_version:
PCI Express Capability is Compliant with Version 1.0 of the PCI Express Spec.
Note:
This capability structure is not compliant with Versions beyond 1.0, since
they require additional capability registers to be reserved. The only purpose
for this capability structure is to make enhanced configuration space
available. Minimizing the size of this structure is accomplished by reporting
version 1.0 compliancy and reporting that this is an integrated root port
device. As such, only three Dwords of configuration space are required for
this structure.
15:8 RO 0x0
next_ptr:
Pointer to the next capability. Set to 0 to indicate there are no more
capability structures.
7:0 RO 0x10
capability_id:
Provides the PCI Express capability ID assigned by PCI-SIG.
Register name Offset Size