Datasheet

Processor Uncore Configuration Registers
164 Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
13.6.1.4 CORECOUNT
Number of Cores
Reflection of the LTCount2 register
13.6.1.5 UBOXERRSTS
This is error status register in the UBOX and covers most of the interrupt related errors.
5:3 RW_LB 0x0
Node Id 1 (NodeId1):
Node Id for group Id 1
2:0 RW_LB 0x0
Node Id 0 (NodeId0):
Node Id for group 0
Type: CFG PortID: N/A
Bus: 1 Device: 11 Function: 0
Offset: 0x54
Bit Attr Default Description
Type: CFG PortID: N/A
Bus: 1 Device: 11 Function: 0
Offset: 0x60
Bit Attr Default Description
31:5 RV - Reserved.
4:0 RO_V 0x0
Core Count (CoreCount):
Reflection of the LTCount2
Type: CFG PortID: N/A
Bus: 1 Device: 11 Function: 0
Offset: 0x64
Bit Attr Default Description
31:24 RV - Reserved.
23:18 RWS_V 0x0
Message Channel Tracker TimeOut (Msg_Ch_Tkr_TimeOut):
Message Channel Tracker TimeOut. This error occurs when any NP request
doesn’t receive response in 4K cycles. The event is SV use and logging only, not
signaling
17:17 RWS_V 0x0
Message Channel Tracker Error (Msg_Ch_Tkr_Err):
This field is don’t care since it no use any more.
16:16 RW_V 0x0
SMI delivery valid (SMI_delivery_valid):
SMI interrupt delivery status valid, write 1'b1 to clear valid status
15:8 RV -
reserved:
reserved
7:7 RWS_V 0x0
MasterLock Timeout received by UBOX (MasterLockTimeOut):
Master Lock Timeout received by UBOX