Datasheet

Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family 167
Datasheet Volume Two: Functional Description, February 2014
Processor Uncore Configuration Registers
13.6.3.2 SMICTRL
SMI generation control.
13.7 Power Controller Unit (PCU) Register
13.7.1 Device 10 Function 0
Type: CFG PortID: N/A
Bus: 1 Device: 11 Function: 3
Offset: 0xd8
Bit Attr Default Description
31:28 RV - Reserved.
27:27 RW_LB 0x0
Mask SMI Generation on Intel QPI Clock/Data Failover (SMIDis3):
Mask SMI generation Intel QPI clock/data failover.
1 - Masked
0 - Unmasked.
Note:
To get SMI for this Intel QPI Clock/Data Failover event, the QPIERRDIS.smi_en
should be set to 1.
26:26 RW_LB 0x1
Mask SMI Generation on Misaligned Access and Lock Timeout (SMIDis2):
Mask SMI generation misaligned access and Lock timeout.
1 - Masked
0 - Unmasked.
25:25 RW_LB 0x0
Mask SMIs Generation for All Errors enabled in UBOXERRCTL (SMIDis):
Mask generation of SMI for ALL errors enabled in UBOXERRCTL register (Except
SMI Time out, bit 6).
1 - Masked.
0 - Unmasked.
If set, will override bits 24 and bit 26.
24:24 RW_LB 0x0
UMC SMI Enable (UMCSMIEn):
This is the enable bit that enables SMI generation due to a UMC.
1 - Generate SMI after the threshold counter expires.
0 - Disable generation of SMI
Need to set 0 in eMCA Gen1 mode.
23:20 RV - Reserved.
19:0 RW_LB 0x0
SMI generation threshold (Threshold):
This is the countdown that happens in the hardware before an SMI is generated
due to a UMC.
Register name Offset Size
VID 0x0 16
DID 0x2 16
PCICMD 0x4 16