Datasheet

Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family 171
Datasheet Volume Two: Functional Description, February 2014
Processor Uncore Configuration Registers
The energy status is reported in units which are defined in
PACKAGE_POWER_SKU_UNIT_MSR[ENERGY_UNIT].
The data is updated by PCU microcode and is Read Only for all SW.
13.7.1.6 PACKAGE_TEMPERATURE
Package temperature in degrees (C). This field is updated by FW.
13.7.1.7 P_STATE_LIMITS
This register allows SW to limit the maximum frequency allowed during run-time.
PCU microcode will sample this register in slow loop.
Functionality added in B-step.
13.7.1.8 TEMPERATURE_TARGET
Legacy register holding temperature related constants for Platform use. This register is
updated by FW.
Type: CFG PortID: N/A
Bus: 1 Device: 10 Function: 0
Offset: 0x90
Bit Attr Default Description
31:0 RO_V 0x0
Energy Value (DATA):
Energy Value
Type: CFG PortID: N/A
Bus: 1 Device: 10 Function: 0
Offset: 0xc8
Bit Attr Default Description
31:8 RV - Reserved.
7:0 RO_V 0x0
Temperature (DATA):
Package temperature in degrees (C).
Type: CFG PortID: N/A
Bus: 1 Device: 10 Function: 0
Offset: 0xd8
Bit Attr Default Description
31:31 RW_KL 0x0
Lock (LOCK):
This bit will lock all settings in this register.
30:16 RV - Reserved.
15:8 RW_L 0x0
P-State Offset (PSTT_OFFSET):
HW P-State control on the relative offset from P1. The offset field determines
the number of bins to drop P1 (dynamically).
7:0 RW_L 0xff
P-State Limitation (PSTT_LIM):
This field indicates the maximum frequency limit allowed during run-time.