Datasheet

Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family 173
Datasheet Volume Two: Functional Description, February 2014
Processor Uncore Configuration Registers
13.7.2.1 SSKPD
Sticky Scratchpad Data.
This register holds 64 writable bits with no functionality behind them. It is for the
convenience of BIOS and graphics drivers.
13.7.2.2 C2C3TT
C2 to C3 Transition Timer.
BIOS can update this value during run-time.
Unit for this register is usec. So we have a range of 0-4095 us.
13.7.2.3 CSR_DESIRED_CORES
Number of cores/threads BIOS wants to exist on the next reset. A processor reset must
be used for this register to take effect. Note, programming this register to a value
higher than the product has cores should not be done.
This register is reset only by PWRGOOD.
Type: CFG PortID: N/A
Bus: 1 Device: 10 Function: 1
Offset: 0x6c
Bit Attr Default Description
63:0 RWS 0x0
Scratchpad Data (SKPD):
4 WORDs of data storage.
Type: CFG PortID: N/A
Bus: 1 Device: 10 Function: 1
Offset: 0x74
Bit Attr Default Description
31:12 RV - Reserved.
11:0 RW 0x32
Pop Down Initialization Value (PPDN_INIT):
Value in micro-seconds.
Type: CFG PortID: N/A
Bus: 1 Device: 10 Function: 1
Offset: 0xa4
Bit Attr Default Description
31:31 RWS_KL 0x0
Lock (LOCK):
Lock:
once written to a “1”, changes to this register cannot be done. Cleared only by
a power-on reset
30:30 RWS_L 0x0
SMT Disable (SMT_DISABLE):
Disable simultaneous multithreading in all cores if this bit is set to “1”.
29:16 RV - Reserved.