Datasheet

Processor Uncore Configuration Registers
174 Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
13.7.3 Device 10 Function 2
15:0 RWS_L 0x0
Cores Off Mask (CORE_OFF_MASK):
BIOS will set this bit to request that the matching core should not be activated
coming out of reset.
The default value of this registers means that all cores are enabled.
Restrictions: At least one core needs to be left active. Otherwise, FW will
ignore the setting altogether.
Register Name Offset Size
VID 0x0 16
DID 0x2 16
PCICMD 0x4 16
PCISTS 0x6 16
RID 0x8 8
CCR 0x9 24
CLSR 0xc 8
PLAT 0xd 8
HDR 0xe 8
BIST 0xf 8
SVID 0x2c 16
SDID 0x2e 16
CAPPTR 0x34 8
INTL 0x3c 8
INTPIN 0x3d 8
MINGNT 0x3e 8
MAXLAT 0x3f 8
PACKAGE_RAPL_PERF_STATUS 0x88 64
DRAM_POWER_INFO 0x90 64
DRAM_ENERGY_STATUS 0xa0 64
DRAM_ENERGY_STATUS_CH0 0xa8 64
DRAM_ENERGY_STATUS_CH1 0xb0 64
DRAM_ENERGY_STATUS_CH2 0xb8 64
DRAM_ENERGY_STATUS_CH3 0xc0 64
DRAM_RAPL_PERF_STATUS 0xd8 64
MCA_ERR_SRC_LOG 0xec 32
THERMTRIP_CONFIG 0xf8 32
Type: CFG PortID: N/A
Bus: 1 Device: 10 Function: 1
Offset: 0xa4
Bit Attr Default Description