Datasheet

Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family 179
Datasheet Volume Two: Functional Description, February 2014
Processor Uncore Configuration Registers
13.7.4.2 CAPID0
This register is a Capability Register used to expose enable/disable for BIOS use.
Type: CFG PortID: N/A
Bus: 1 Device: 10 Function: 3
Offset: 0x80
Bit Attr Default Description
31:28 RV - Reserved.
27:24 RO_FW 0x1
CAPID_Version:
This field has the value 0001b to identify the first revision of the CAPID register
definition.
23:16 RO_FW 0x18
CAPID_Length:
This field indicates the structure length including the header in Bytes.
15:8 RO_FW 0x0
Next_Cap_Ptr:
This field is hardwired to 00h indicating the end of the capabilities linked list.
7:0 RO_FW 0x9
CAP_ID:
This field has the value 1001b to identify the CAP_ID assigned by the PCI SIG
for vendor dependent capability pointers.
Type: CFG PortID: N/A
Bus: 1 Device: 10 Function: 3
Offset: 0x84
Bit Attr Default Description
31:31 RO_FW 0x0
PCLMULQ_DIS:
Disable PCLMULQ instructions
30:30 RO_FW 0x0
DCU_MODE:
DCU mode
0: normal
1: 16K 1/2 size ECC mode
29:29 RO_FW 0x0
PECI_EN:
Enable PECI to the Processor
28:28 RO_FW 0x0
ART_DIS:
SparDisable support for Always Running APIC Timer.
Disable the ART (Always Running APIC Timer) function in the APIC (enable
legacy timer)
27:27 RO_FW 0x0
SLC64_DIS:
Disable Segment-Limit Checking 64-Bit Mode - Segment limit checks also in
long mode (currently only supported in compatibility mode)
26:26 RO_FW 0x0
GSSE256_DIS:
Disable all GSSE instructions and Disables setting GSSE XFeatureEnabledMask
[GSSE] bit.
25:25 RO_FW 0x0
XSAVEOPT_DIS:
Disable XSAVEOPT.