Datasheet

Overview
18 Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
— One Intel® C102/C104 Scalable Memory Buffer per Intel SMI2 channel, with up
to two DDR3 channels per Intel C102/C104 Scalable Memory Buffer and up to
eight DDR3 channels per socket.
— Supports 1067, 1333 and 1600 MT/s DDR3 frequencies.
— Supports up to 3 DIMMs per DDR3 channel.
—Supports 2GB, 4GB and 8GB DRAM technologies
• PCI Express* interfaces: Up to 32 lanes each operating at PCI Express 3.0 speed
(PCIe* 3.0) and 4 lanes of DMI2/PCI Express 2.0 (PCIe* 2.0) interface.
• Supports C states C0, C1, C3 and C6.
• Advanced Reliability Features
• Platform Technologies supported are Intel
®
Turbo Boost Technology, Intel
®
Trusted
Execution Technology (Intel
®
TXT), Intel
®
Dynamic Power, Intel
®
Virtualization
Technology (Intel
®
VT) for IA-32, Intel
®
64 and Intel® Architecture (Intel
®
VT-x),
Intel VT for Directed I/O (Intel
®
VT-d), Intel
®
I/O Acceleration Technology (Intel
®
I/OAT)/CB3, Intel
®
Intelligent Power Node Manager, TPM 1.2, Digital RNG,
and more.
1.2 Terminology
A ‘_N’ symbol after a signal name refers to an active low signal, indicating a signal is in
the active state when driven to a low level. For example, when RESET_N is low, a reset
has been requested.
Table 1-1. Processor Terminology (Sheet 1 of 4)
Term Description
ASPM Active State Power Management
BMC Baseboard Management Controller
Cbo Cache and Core Box. It is a term used for internal logic providing ring interface to
LLC and Core.
DCU Data Cache Unit
DDR3 Third generation Double Data Rate SDRAM memory technology that is the
successor to DDR2 SDRAM
DMA Direct Memory Access
DMI2 Direct Media Interface operating at PCI Express* 2.0 speed.
DSB Data Stream Buffer. This is part of the Intel Xeon processor E7 v2 product family
core architecture.
DTLB Data Translation Look-aside Buffer. Part of the Intel Xeon processor E7 v2
product family core architecture.
DTS Digital Thermal Sensor
ECC Error Correction Code
Enhanced Intel
SpeedStep
®
Technology
Allows the operating system to reduce power consumption when performance is
not needed.
Execute Disable Bit The Execute Disable bit allows memory to be marked as executable or non-
executable, when combined with a supporting operating system. If code
attempts to run in non-executable memory the processor raises an error to the
operating system. This feature can prevent some classes of viruses or worms
that exploit buffer overrun vulnerabilities and can thus help improve the overall
security of the system. See the Intel
®
64 and IA-32 Architectures Software
Developer's Manuals for more detailed information.
Flit Flow Control Unit. Data transfer unit of Intel QPI Link Layer. 1 Flit = 80-bits.