Datasheet

Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family 189
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14 Integrated I/O (IIO)
Configuration Registers
14.1 Registers Overview
14.1.1 Configuration Registers (CSR)
There are two distinct CSR register spaces supported by the IIO Module.
The first one is the traditional PCI-defined configuration registers. These registers are
accessed via the well known configuration transaction mechanism defined in the PCI
specification and this uses the bus:device:function number concept to address a
specific device’s configuration space. Accesses to PCI configuration registers is
achieved via NcCfgRd/Wr transactions on Intel
®
QPI.
The second is via MMIO space for Intel® Quick Data DMA, Intel
®
VT-d, RCRB and
I/OxAPIC runtime registers. These memory-mapped accesses use the
NcWrPtl/NcRd/NcRdPtl transactions on Intel
®
QPI.
14.1.2 BDF:BAR# for various MMIO BARs in IIO
This is needed for any entity trying to access MMIO registers in the IIO module over
message channel.
14.1.3 Unimplemented Devices/Functions and Registers
If the IIO module receives a configuration access over message channel or directly via
the JTAG miniport, to a device/function or BAR# that does not exist in the IIO module,
the IIO module will abort these accesses. Software should not attempt or rely on reads
or writes to unimplemented registers or register bits.
Table 14-1. BDF:BAR# for various MMIO BARs in IIO
BAR name B D F BAR#
DMIRCBAR DC 0 0 0
Quick Data DMA-BAR0 DC 4 0 0
Quick Data DMA-BAR1 DC 4 1 0
Quick Data DMA-BAR2 DC 4 2 0
Quick Data DMA-BAR3 DC 4 3 0
Quick Data DMA-BAR4 DC 4 4 0
Quick Data DMA-BAR5 DC 4 5 0
Quick Data DMA-BAR6 DC 4 6 0
Quick Data DMA-BAR7 DC 4 7 0
VT-d VTBAR DC 5 0 0
I/OxAPIC-MBAR DC 5 4 0
I/OxAPIC-ABAR DC 5 4 1