Datasheet

Integrated I/O (IIO) Configuration Registers
190 Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
14.1.4 PCI Vs. PCIe* Device / Function
PCI devices/functions do NOT have a PCIe* capability register set and do not decode
offsets 100h and beyond. Accesses to 100h and beyond are master aborted by these
devices. I/OxAPIC functions are PCI functions. All other functions in the IIO module are
PCIe* functions and these have a PCIe* capability register set and also decode address
offsets 100h and beyond.
14.2 Device 0 Function 0 DMI, Device 0
Function 0 PCIe*, Device 2 Function 0-3 PCIe*,
Device 3 Function 0-3 PCIe*
Intel Xeon processor E7-2800/4800/8800 v2 product family does not have Port 1
(Device 1) and does not support Non Transparent Bridge (NTB) Mode.
Device 0 Function 0 PCIe* Mode - Port 0 (X4)
Device 2 - Port 2 (X16)
Device 3 - Port 3 (X16)
Table 14-2. Function number of active root ports in port 2(Dev#2) based on port
bifurcation
Port bifurcation
Function# of Active Root Port
15:12 11:8 7:4 3:0
x16 0
x8x8 2 0
x8x4x4 2 1 0
x4x4x8 3 2 0
x4x4x4x4 3 2 1 0
Table 14-3. Function number of active root ports in port 3(Dev#3) based on port
bifurcation
Port bifurcation
Function# of active root port
15:12 11:8 7:4 3:0
x16 0
x8x8 2 0
x8x4x4 2 1 0
x4x4x8 3 2 0
x4x4x4x4 3 2 1 0
Register name Offset Size
Device 0
function
Device 2
function
Device 3
function
VID 0x0 16 0 0 - 3 0 - 3
DID 0x2 16 0 0 - 3 0 - 3
PCICMD 0x4 16 0 0 - 3 0 - 3
PCISTS 0x6 16 0 0 - 3 0 - 3