Datasheet

Integrated I/O (IIO) Configuration Registers
204 Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
14.2.16 SECSTS
Secondary Status Register.
1:0 RO 0x0
i_o_address_limit_capability:
IIO only supports 16 bit addressing
Type: CFG PortID: N/A
Bus: 0 Device: 0Function:0 (PCIe* Mode)
Bus: 0 Device: 2Function:0-3
Bus: 0 Device: 3Function:0-3
Offset: 0x1d
Bit Attr Default Description
Type: CFG PortID: N/A
Bus: 0 Device: 0Function:0 (PCIe* Mode)
Bus: 0 Device: 2Function:0-3
Bus: 0 Device: 3Function:0-3
Offset: 0x1e
Bit Attr Default Description
15:15 RW1C 0x0
dpe:
Detected Parity Error
This bit is set by the root port whenever it receives a poisoned TLP in the PCI
Express port. This bit is set regardless of the state the Parity Error Response
Enable bit in the Bridge Control register.
14:14 RW1C 0x0
rse:
Received System Error
This bit is set by the root port when it receives a ERR_FATAL or
ERR_NONFATAL message from PCI Express. Note this does not include the
virtual ERR* messages that are internally generated from the root port when
it detects an error on its own.
13:13 RW1C 0x0
rma:
Received Master Abort Status
This bit is set when the root port receives a Completion with ’Unsupported
Request Completion’ Status or when the root port master aborts a Type0
configuration packet that has a nonzero device number.
12:12 RW1C 0x0
rta:
Received Target Abort Status
This bit is set when the root port receives a Completion with ’Completer
Abort’ Status.
11:11 RW1C 0x0
sta:
Signaled Target Abort
This bit is set when the root port sends a completion packet with a
’Completer Abort’ Status (including peer-to-peer completions that are
forwarded from one port to another).
10:9 RO 0x0
devsel_timing:
Not applicable to PCI Express. Hardwired to 0.