Datasheet

Integrated I/O (IIO) Configuration Registers
208 Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
14.2.22 PLIMU
Prefetchable Memory Limit Upper 32 bits.
14.2.23 CAPPTR
Capability Pointer.
Type: CFG PortID: N/A
Bus: 0 Device: 0Function:0 (PCIe* Mode)
Bus: 0 Device: 2Function:0-3
Bus: 0 Device: 3Function:0-3
Offset: 0x2c
Bit Attr Default Description
31:0 RW 0x0
prefetchable_upper_32_bit_memory_limit_address:
Corresponds to A[63:32] of the prefetchable memory address range’s limit
address of the PCI Express port.The Prefetchable Memory Base and Memory
Limit registers define a memory mapped I/O prefetchable address range (64-
bit addresses) which is used by the PCI Express bridge to determine when to
forward memory transactions based on the following formula:
PREFETCH_MEMORY_BASE_UPPER :: PREFETCH_MEMORY_BASE <= A[63:20]
<= PREFETCH_MEMORY_LIMIT_UPPER :: PREFETCH_MEMORY_LIMIT
The upper 12 bits of both the Prefetchable Memory Base and Memory Limit
registers are read/write and corresponds to the upper 12 address bits,
A[31:20] of 32-bit addresses. The bottom of the defined memory address
range will be aligned to a 1 MB boundary and the top of the defined memory
address range will be one less than a 1 MB boundary.
The bottom 4 bits of both the Prefetchable Memory Base and Prefetchable
Memory Limit registers are read-only, contain the same value, and encode
whether or not the bridge supports 64-bit addresses.
If these four bits have the value 0h, then the bridge supports only 32 bit
addresses.
If these four bits have the value 1h, then the bridge supports 64-bit addresses
and the Prefetchable Base Upper 32 Bits and Prefetchable Limit Upper 32 Bits
registers hold the rest of the 64-bit prefetchable base and limit addresses
respectively.
Setting the prefetchable memory limit less than prefetchable memory base
disables the 64-bit prefetchable memory range altogether.
Notes:
In general the memory base and limit registers won’t be programmed by
software without clearing the MSE bit first.
Type: CFG PortID: N/A
Bus: 0 Device: 0Function:0
Bus: 0 Device: 2Function:0-3
Bus: 0 Device: 3Function:0-3
Offset: 0x34
Bit Attr Default Description
7:0
RO_V (Device 0
Function 0, Device 2
Function 0-3)
RW_V (Device 3
Function 0)
RO (Device 3
Function 1-3)
0x40
0x60 (Device 3
Function 0)
0x90 (Device 0
Function 0)
capability_pointer:
Points to the first capability structure for the device
In DMI mode, it points to the PCIe* capability.
In PCIe* mode, it points to the SVID/SDID capability.