Datasheet

Integrated I/O (IIO) Configuration Registers
218 Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
14.2.42 DEVCAP
The PCI Express Device Capabilities register identifies device specific information for
the device.
Type: CFG PortID: N/A
Bus: 0 Device: 0Function:0
Bus: 0 Device: 2Function:0-3
Bus: 0 Device: 3Function:0-3
Offset: 0x94
Bit Attr Default Description
31:28 RV - Reserved.
27:26 RO 0x0
captured_slot_power_limit_scale:
Does not apply to root ports or integrated devices.
25:18 RO 0x0
captured_slot_power_limit_value:
Does not apply to root ports or integrated devices.
15:15 RO 0x1
role_based_error_reporting:
IIO is 1.1 compliant and so supports this feature
14:14 RO 0x0
power_indicator_present_on_device:
Does not apply to root ports or integrated devices.
13:13 RO 0x0
attention_indicator_present:
Does not apply to root ports or integrated devices.
12:12 RO 0x0
attention_button_present:
Does not apply to root ports or integrated devices.
11:9 RO 0x0
endpoint_l1_acceptable_latency:
Does not apply to IIO RCiEP (link does not exist between host and
RCiEP)
8:6 RO 0x0
endpoint_l0s_acceptable_latency:
Does not apply to IIO RCiEP (link does not exist between host and
RCiEP)
5:5 RW_O
0x0
0x1 (Device 3
Function 0)
extended_tag_field_supported:
Not Supported.
4:3 RO 0x0
phantom_functions_supported:
IIO does not support phantom functions.
2:0 RO
0x1
0x0 (Device 0
Function 0)
max_payload_size_supported:
Max payload is 128B on the DMI/PCIe* port corresponding to Port 0.
Support 256B payload on PCI Express Ports 2 and 3.