Datasheet

Integrated I/O (IIO) Configuration Registers
238 Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
14.2.55 DEVCTRL2
PCI Express Device Control Register 2.
3:0 RO 0xe
cmpltovalsup:
Completion Timeout Values Supported
This field indicates device support for the optional Completion Timeout
programmability mechanism. This mechanism allows system software to
modify the Completion Timeout range. Bits are one-hot encoded and set
according to the table below to show timeout value ranges supported. A
device that supports the optional capability of Completion Timeout
Programmability must set at least two bits.Four time values ranges are
defined:
Range A: 50 us to 10 ms
Range B: 10 ms to 250 ms
Range C: 250 ms to 4 s
Range D: 4 s to 64 s
Bits are set according to table below to show timeout value ranges
supported.
0000b: Completions Timeout programming not supported – values is fixed by
implementation in the range 50 us to 50 ms.
0001b: Range A
0010b: Range B
0011b: Range A & B
0110b: Range B & C
0111b: Range A, B, & C
1110b: Range B, C D
1111b: Range A, B, C & D
All other values are reserved.
IIO supports timeout values up to 10 ms-64 s
Type: CFG PortID: N/A
Bus: 0 Device: 0Function:0
Bus: 0 Device: 2Function:0-3
Bus: 0 Device: 3Function:0-3
Offset: 0xb4
Bit Attr Default Description
Type: CFG PortID: N/A
Bus: 0 Device: 0Function:0 (DMI2 Mode)
Offset: 0xf8
Bus: 0 Device: 0Function:0 (PCIe* Mode)
Bus: 0 Device: 2Function:0-3
Bus: 0 Device: 3Function:0-3
Offset: 0xb8
Bit Attr Default Description
15:8 RV - Reserved.
7:7 RO 0x0 atomicegressblock:
6:6 RO 0x0 atomicreqen:
5:5 RW_L 0x0
ari:
Alternative RID InterpretationEnable
Applies only to root ports. When set to 1b, ARI is enabled
for the Root Port. For Device#0 in DMI mode, this bit is
ignored