Datasheet

The Processor Architecture Overview
24 Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
2.1.1 Frequency
The processor cores are designed to run at a rated frequency and the architecture
allows operating at lower frequencies in order to make appropriate power/performance
trade-off. Along with the ability to slow down cores for power optimization, “Intel Turbo
Boost Technology” allows the ability to increase a core’s speed to optimize single
threaded applications.
2.1.2 Caching Hierarchy
Caching for the processor spans three levels - dedicated instruction and data cache
(ICU and DCU), mid-level cache (MLC) for each core, and last level cache (LLC) for the
socket.
• ICU and DCU: 32 KB each
• MLC per core: 256 KB (instructions and data)
• LLC per socket: Up to 37.5 MB (instructions and data)
— Each core slice brings 2.5 MB slices
2.1.3 Addressing Space
The processor supports a virtual address space of 48 bits and a physical address space
of 46 bits.
2.1.4 Multi-threaded Cores
Each core supports two threads.
2.1.5 Power Management
The processor core implements a number of energy efficiency features. Additionally,
the processor implements a sophisticated power management scheme to throttle
cores and the memory traffic of each memory controller independently through
internal protocols.
2.1.6 Intel
®
Technologies
The processor core offers several key Intel
®
Technologies. Table 2-1 enumerates the
key technologies implemented in the processor core.
Table 2-1. Technologies in the Processor Core
Abbreviated Name Short Description
GSSE Extension of the SSE/SSE2 floating point instruction set to 256b operands.
Xsave/Xrestore
New instructions to streamline OS/VMM support for features with new state.
Better software control over state saved, restored and initialized.
Intel
®
Advanced Encryption
Standard New Instructions
(Intel
®
AES-NI)
Speed up encryption tasks to enable broader Intel AES-NI use.
OS/VMM Features Real mode Intel VT support. Always running timer enabling “tick-less” OS
1 GB large page support Support for larger 1 GB pages in server applications.
Intel TXT for servers Server-focused security technology.