Datasheet

Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family 245
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.2.60 PMCSR
Power Management Control and Status Register
This register provides status and control information for PM events in the PCI Express
port of the IIO.
Type: CFG PortID: N/A
Bus: 0 Device: 0Function:0
Bus: 0 Device: 2Function:0-3
Bus: 0 Device: 3Function:0-3
Offset: 0xe4
Bit Attr Default Description
31:24 RO 0x0
data:
Not relevant for I/OxAPIC
23:23 RO 0x0
bus_power_clock_control_enable:
Not relevant for I/OxAPIC
22:22 RO 0x0
b2_b3_support:
Not relevant for I/OxAPIC
21:16 RV - Reserved.
15:15 RW1CS 0x0
pme_status:
Not relevant for I/OxAPIC
14:13 RO 0x0
data_scale:
Not relevant for I/OxAPIC
12:9 RO 0x0
data_select:
Not relevant for I/OxAPIC
8:8
RWS
RWS_L (Device 3
Function 0)
0x0
pme_enable:
Not relevant for I/OxAPIC
7:4 RV - Reserved.
3:3 RW_O 0x1
no_soft_reset:
Indicates I/OxAPIC does not reset its registers when transitioning
from D3hot to D0.
2:2 RV - Reserved.