Datasheet

Integrated I/O (IIO) Configuration Registers
262 Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
20:20 RW 0x1
maltlp_32baddr64bhdr_en:
When set, enables reporting a Malformed packet when the
TLP is a 32 bit address in a 4DW header. PCI Express
forbids using 4DW header sizes when the address is less
than 4 GB, but some cards may use the 4DW header
anyway. In these cases, the upper 32 bits of address are all
0.
19:19 RV - Reserved.
18:18 RWS 0x0
max_read_completion_combine_size:
When set, all completions are returned without combining.
Completions are naturally broken on cacheline boundaries,
so all completions will be 64B or less.
17:16 RV 0x0
Reserved1:
Reserved. BIOS should not change the value in this field.
15:15 RWS 0x0 dis_hdr_storage:
14:14 RWS 0x0 allow_one_np_os:
13:13 RWS 0x0
tlp_on_any_lane:
BIOS should not change the value in this field.
12:12 RWS 0x1 disable_ob_parity_check:
11:11 RWS 0x1
allow_1nonvc1_after_10vc1s:
Allow a non-VC1 request from DMI to go after every ten
VC1 request (to prevent starvation of non-VC1).
Only avaiable for Device 0 Function 0.
10:10 RV - Reserved.
9:9 RWS 0x0
dispdspolling:
Disables gen2 if timeout happens in polling.cfg.
8:7 RW 0x0 pme2acktoctrl:
6:6 RW 0x0
enable_timeout_for_receiving_pme_to_ack:
When set, IIO enables the timeout to receiving the
PME_TO_ACK
5:5 RW_V 0x0
send_pme_turn_off_message:
When this bit is written with a 1b, IIO sends a
PME_TURN_OFF message to the PCIe* link. Hardware
clears this bit when the message has been sent on the link.
Type: CFG PortID: N/A
Bus: 0 Device: 0Function:0
Bus: 0 Device: 2Function:0-3
Bus: 0 Device: 3Function:0-3
Offset: 0x188
Bit Attr Default Description