Datasheet

Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family 269
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.2.92 CTOCTRL
Completion Timeout Control.
14.2.93 XPCORERRSTS
XP Correctable Error Status
The contents of the next set of registers - XPCORERRSTS, XPCORERRMSK,
XPUNCERRSTS, XPUNCERRMSK, XPUNCERRSEV, XPUNCERRPTR. The architecture
model for error logging and escalation of internal errors is similar to that of PCI Express
AER, except that these internal errors never trigger an MSI and are always reported to
1:1 RW 0x0
cause_rcverr:
Cause a Receiver Error
When this bit is written to transition from 0 to 1, one and only one error
assertion pulse is produced on the error source signal for the given port. This
error will appear equivalent to an actual error assertion because this event is
OR’d into the existing error reporting structure. To log another error, this bit
must be cleared first, before setting again. Leaving this bit in a 1 state does
not produce a persistent error condition.
Note:
This bit is used for an correctable error test
This bit must be cleared by software before creating another event.
This bit is disabled by bit 0 of this register
0:0 RW_O 0x0
errinjdis:
Error Injection Disable
This bit disables the use of the PCIe* error injection bits.
Note:
This is a write once bit.
Type: CFG PortID: N/A
Bus: 0 Device: 0Function:0
Bus: 0 Device: 2Function:0-3
Bus: 0 Device: 3Function:0-3
Offset: 0x1d8
Bit Attr Default Description
Type: CFG PortID: N/A
Bus: 0 Device: 0Function:0
Bus: 0 Device: 2Function:0-3
Bus: 0 Device: 3Function:0-3
Offset: 0x1e0
Bit Attr Default Description
31:10 RV - Reserved.
9:8 RW 0x0
xp_to_pcie_timeout_select:
When OS selects a timeout range of 17s to 64s for XP (that affect NP tx
issued to the PCIe/DMI) using the root port’s DEVCTRL2 register, this field
selects the subrange within that larger range, for additional controllability.
00 : 17s-30s
01 : 31s-45s
10 : 46s-64s
11 : Reserved
7:0 RV - Reserved.