Datasheet

Integrated I/O (IIO) Configuration Registers
270 Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
the system software. Mask bits mask the reporting of an error and severity bit controls
escalation to either fatal or nonfatal error to the internal core error logic. Note that
internal errors detected in the PCI Express cluster are not dependent on any other
control bits for error escalation other than the mask bit defined in these registers. All
these registers are sticky.
14.2.94 XPCORERRMSK
XP Correctable Error Mask.
14.2.95 XPUNCERRSTS
XP Uncorrectable Error Status.
Type: CFG PortID: N/A
Bus: 0 Device: 0Function:0
Bus: 0 Device: 2Function:0-3
Bus: 0 Device: 3Function:0-3
Offset: 0x200
Bit Attr Default Description
31:1 RV - Reserved.
0:0 RW1CS 0x0
pci_link_bandwidth_changed_status:
This bit is set when the logical OR of LNKSTS[15] and LNKSTS[14] goes from
0 to 1.
Type: CFG PortID: N/A
Bus: 0 Device: 0Function:0
Bus: 0 Device: 2Function:0-3
Bus: 0 Device: 3Function:0-3
Offset: 0x204
Bit Attr Default Description
31:1 RV - Reserved.
0:0 RWS 0x0
pci_link_bandwidth_changed_mask:
Masks the BW change event from being propagated to the IIO core error logic
as a correctable error
Type: CFG PortID: N/A
Bus: 0 Device: 0Function:0
Bus: 0 Device: 2Function:0-3
Bus: 0 Device: 3Function:0-3
Offset: 0x208
Bit Attr Default Description
31:10 RV - Reserved.
9:9 RW1CS 0x0
outbound_poisoned_data:
Set when outbound poisoned data (from Intel
®
QPI or peer, write or read
completion) is received by this port
8:8 RW1CS 0x0 received_msi_writes_greater_than_a_dword_data:
7:7 RV -
Reserved3:
Reserved
6:6 RW1CS 0x0 received_pcie_completion_with_ur_status:
5:5 RW1CS 0x0 received_pcie_completion_with_ca_status: