Datasheet

Integrated I/O (IIO) Configuration Registers
326 Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
23:23 RO 0x0
bus_power_clock_control_enable:
Not relevant for I/OxAPIC
22:22 RO 0x0
b2_b3_support:
Not relevant for I/OxAPIC
21:16 RV - Reserved.
15:15 RO 0x0
pme_status:
Not relevant for I/OxAPIC
14:13 RO 0x0
data_scale:
Not relevant for I/OxAPIC
12:9 RO 0x0
data_select:
Not relevant for I/OxAPIC
8:8 RO 0x0
pme_enable:
Not relevant for I/OxAPIC
7:4 RV - Reserved.
3:3 RO 0x1
no_soft_reset:
Indicates I/OxAPIC does not reset its registers when transitioning from
D3hot to D0.
2:2 RV - Reserved.
1:0 RW_V 0x0
power_state:
This 2-bit field is used to determine the current power state of the function
and to set a new power state as well.
00: D0
01: D1 (not supported by IOAPIC)
10: D2 (not supported by IOAPIC)
11: D3_hot
If Software tries to write 01 or 10 to this field, the power state does not
change from the existing power state which is either (D0 or D3_hot) and nor
do these bits[1:0] change value.
When in D3_hot state, I/OxAPIC will
a) respond to only Type 0 configuration transactions targeted at the device’s
configuration space, when in D3_hot state
c) will not respond to memory that is, D3hot state is equivalent to MSE,
accesses to MBAR region note: ABAR region access still go through in
D3_hot state, if it enabled
d) will not generate any MSI writes
Type: CFG PortID: N/A
Bus: 0 Device: 4Function:0-7
Offset: 0xe4
Bit Attr Default Description