Datasheet

Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family 337
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.5.7 INTRDELAY
Interrupt Delay.
14.5.8 CS_STATUS
Chipset Status.
14.5.9 DMACAPABILITY
Type: MEM PortID: 8’h7e
Bus: 0 Device: 4Function:0-7
Offset: 0xc
Bit Attr Default Description
15:15 RO 0x1
interrupt_coalescing_supported:
The IIO does support interrupt coalescing by delaying interrupt generation.
14:14 RV - Reserved.
13:0 RW 0x0
interrupt_delay_time:
Specifies the number of microseconds that the IIO delays generation of an
interrupt (legacy or MSI or MSI-X) from the time that interrupts are enabled
(that is,, Master Interrupt Enable bit in the CSIPINTRCTRL register is set or,
for MSI-X when Vector Control bit=1, when CHANCTRL:Interrupt Disable for
that channel is reset).
Type: MEM PortID: 8’h7e
Bus: 0 Device: 4Function:0-7
Offset: 0xe
Bit Attr Default Description
15:4 RV - Reserved.
3:3 RO 0x0
address_remapping:
This bit reflects the TE bit of the non-VC1 Intel
®
VT-d engine
2:2 RO 0x0 memory_bypass:
1:1 RO 0x0 mmio_restriction:
0:0 RV - Reserved.
Type: MEM PortID: 8’h7e
Bus: 0 Device: 4Function:0-7
Offset: 0x10
Bit Attr Default Description
31:10 RV - Reserved.